Surface Uniformity of Wafer-Scale 4H-SiC Epitaxial Layers Grown under Various Epitaxial Conditions

Abstract

Wide band gap semiconductor 4H-SiC is currently widely used in the manufacture of high-frequency and high-voltage power devices. The size of commercial 4H-SiC wafers is increasing, from 4 inches to 6 inches. Surface roughness, as one of the parameters reflecting the quality of epitaxial wafers, is closely related to the performance of power devices. Most studies on the uniformity of epitaxial layers did not focus on RMS; however, the uniformity of epitaxial surface roughness also affects the device yield. In this paper, the root mean square roughness (RMS) and uniformity (σ) of epitaxial wafers are investigated as a function of epitaxy conditions, including C/Si ratio, growth temperature, and Si/H ratio. It was found that the best values of RMS and σ were obtained with C/Si ratio = 1 in the experimental range. Growth temperature had opposite effects on RMS and σ, with better RMS uniformity obtained at lower growth temperatures. An insignificant effect on RMS and σ has been found with the Si/H ratio changes in the experimental range. We hope that our experiments can play a certain role in promoting the improvement of the surface roughness of wafer-scale 4H-SiC epitaxial layers.

Silicon Carbide Thin Film Technologies: Recent Advances in Processing, Properties, and Applications - Part I Thermal and Plasma CVD

“…9,49,50 ✓Non-stoichiometric SiCx, 4H-SiC epitaxial layers on n-type 4H-SiC with Si-terminated (0001) faces, with an off-angle of 4°a long the (0001) crystal direction for high-temperature, highvoltage, and high-power devices. 7,33 ✓In-situ SiCN cap layer for AlGaN/GaN high-electron mobility transistors (HEMTs) in high-power and high-frequency electronics. 34 ✓H-free stoichiometric SiC thin films for power electronics.…”

Influence of Growth Process on Suppression of Surface Morphological Defects in 4H-SiC Homoepitaxial Layers

“…With the gradual advancement of silicon carbide (SiC) chemical vapor deposition (CVD) technology, the SiC growth process has approached maturity, and the primary obstacle to producing SiC semiconductor epitaxial wafers lie in the presence of epitaxial defects. These defects pose significant challenges for high-voltage and high-power SiC power electronic devices [ 1 , 2 , 3 , 4 , 5 , 6 , 7 ]. The origins of these defects are often related to many factors, such as substrate quality, growth temperature and cavity structure, and the crystal structure of these defects is usually complicated [ 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 ].…”