Surface electrode ion trap is one of the key devices in modern ion trapping apparatus to host the ion qubits to perform quantum computation. Surface traps fabricated on silicon substrate have the versatility for complex electrode fabrication with 3D integration capability. However, Si induced dielectric loss needs to considered for trap design and the additional ground structure is necessarily incorporated into the surface electrodes fabrication. In this work, surface electrode ion trap is fabricated using standard Cu back end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: (1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes, (2) the use of dry etching to form the fine gap oxide trench between the electrodes for reducing the charge induced stray electric field, (3) the use of Cu mesh ground structure to enhance the resonance performance of the trap, and (4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties is obtained from the fabricated ion trap, with leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with RF line widths of 80 and 40 μm are evaluated for their resonance performances without and with ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with output power increment of 11 and 13 dBm and Q factor increment of 2 and 6, for the corresponding trap types.