Suppression of the Floating-Body Effect of Vertical-Cell DRAM With the Buried Body Engineering Method

Vertical cell transistor is necessary to drastically reduce the chip size of the dynamic random access memory. This structure has a great advantage in terms of shrinkage, but it also has the disadvantage of increasing the OFF-state current by causing floating body effect (FBE). For the first time, it is demonstrated that a stretched tunnelling diode, which consists of a p + layer next to the n + active layer in the buried body, leads to a drastically suppressed FBE. The OFF-state current is sharply reduced by about seven orders compared with a conventional structure. Furthermore, the decrease in the OFF-state current is at minimum when the length of the stretched p + region is approximately half the channel length (L p /L=1/2).

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“…Fig. 2 is a virtual scanning electron microscope (VSEM) picture of the Si column of the measured CBC structure [6]. In Fig.…”

Section: Resultsmentioning

confidence: 99%

Stretched tunnelling body contact structure for suppressing the FBE in a vertical cell DRAM

et al. 2019

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“…The 2 nm technology nodes Samsung, Intel, and TSMC will all have the architecture of gate-all-around field effect transistors (GAAFETs) [ 2 , 3 , 4 , 5 ]. The dynamic random-access memory (DRAM) roadmap of the International Roadmap for Devices and Systems (IRDS) 2020 report proposes that the cell transistor structure of DRAM will shift from one of the current mainstream Saddle Fin to the vertical channel transistor (VCT) [ 6 , 7 , 8 , 9 , 10 , 11 ]. In logic applications, IBM and Samsung jointly proposed vertical-transport FET (VTFET), which achieved a 40 nm contacted gate pitch (CGP) under excellent gate control, which is significantly lower than the 45 nm CGP of the TSMC 3 nm fin field-effect transistor (FinFET) technology node [ 12 , 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale

Chen

Zhu

Wang³

et al. 2023

Nanomaterials

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At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

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“…However, the scaling of the lateral device has become more and more difficult, and the cost of tape-out has become unaffordable for major design houses. At the same time, vertical devices will be competitive candidates for 4F 2 cell transistors in the future DRAM device [9][10][11][12][13]. There are many research reports on vertical devices, which can be divided into two routes.…”

Section: Introductionmentioning

confidence: 99%

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing

Chen

Zhu

Wang³

et al. 2023

Nanomaterials

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Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

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Suppression of the Floating-Body Effect of Vertical-Cell DRAM With the Buried Body Engineering Method

Cited by 12 publications

References 14 publications

Stretched tunnelling body contact structure for suppressing the FBE in a vertical cell DRAM

Stretched tunnelling body contact structure for suppressing the FBE in a vertical cell DRAM

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing

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