Stretched tunnelling body contact structure for suppressing the FBE in a vertical cell DRAM

Abstract

Vertical cell transistor is necessary to drastically reduce the chip size of the dynamic random access memory. This structure has a great advantage in terms of shrinkage, but it also has the disadvantage of increasing the OFF-state current by causing floating body effect (FBE). For the first time, it is demonstrated that a stretched tunnelling diode, which consists of a p + layer next to the n + active layer in the buried body, leads to a drastically suppressed FBE. The OFF-state current is sharply reduced by about seven orders compared with a conventional structure. Furthermore, the decrease in the OFF-state current is at minimum when the length of the stretched p + region is approximately half the channel length (L p /L=1/2).

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“…The 2 nm technology nodes Samsung, Intel, and TSMC will all have the architecture of gate-all-around field effect transistors (GAAFETs) [ 2 , 3 , 4 , 5 ]. The dynamic random-access memory (DRAM) roadmap of the International Roadmap for Devices and Systems (IRDS) 2020 report proposes that the cell transistor structure of DRAM will shift from one of the current mainstream Saddle Fin to the vertical channel transistor (VCT) [ 6 , 7 , 8 , 9 , 10 , 11 ]. In logic applications, IBM and Samsung jointly proposed vertical-transport FET (VTFET), which achieved a 40 nm contacted gate pitch (CGP) under excellent gate control, which is significantly lower than the 45 nm CGP of the TSMC 3 nm fin field-effect transistor (FinFET) technology node [ 12 , 13 , 14 ].…”

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“…However, the scaling of the lateral device has become more and more difficult, and the cost of tape-out has become unaffordable for major design houses. At the same time, vertical devices will be competitive candidates for 4F 2 cell transistors in the future DRAM device [9][10][11][12][13]. There are many research reports on vertical devices, which can be divided into two routes.…”