Abstract:We have demonstrated the suppression of short-channel effects (SCEs) in normally-off GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with deep recessed-gate structures. TCAD simulation results show that the electric field concentration is effectively reduced at the recessed edge of MOSFETs with deeper recessed-gate structures. To demonstrate suppression of SCEs, MOSFET gate structures with recess depths ranging from 45 to 165 nm were fabricated and evaluated. Experimental results show that dee… Show more
“…Using negative Capacitance FINFET [31], using dual metal gate [32,33] the SCEs can be suppressed but these requires complex fabrication processes. Gate recess [34,35] can be another solution although an optimised approach should be used in this case to avoid the leakage.…”
In this paper, we have characterized an AlGaN/GaN High Electron Mobility Transistor (HEMT) with a short gate length (Lg ≈ 0.15μm). We have studied the effect of short gate length on the small signal parameters, linearity parameters and gm-gd ratio in GaN HEMT devices. To understand how scaling results in the variation of the above-mentioned parameters a comparative study with higher gate length devices on similar heterostructure is also presented here. We have scaled down the gate length but the barrier thickness(tbar) remained same which affects the aspect ratio (Lg/tbar) of the device and its inseparable consequences are the prominent short channel effects (SCEs) barring the optimum output performance of the device. These interesting phenomena were studied in detail and explored over a temperature range of -40 oC to 80 oC. To the best of our knowledge this paper explores temperature dependence of SCEs of GaN HEMT for the first time. With an approach to reduce the impact of SCEs a simulation study in Silvaco TCAD was carried out and it is observed that a recessed gate structure on conventional heterostructure successfully reduces SCEs and improves RF performance of the device. This work gives an overall view of gate length scaling on conventional AlGaN/GaN HEMTs.
“…Using negative Capacitance FINFET [31], using dual metal gate [32,33] the SCEs can be suppressed but these requires complex fabrication processes. Gate recess [34,35] can be another solution although an optimised approach should be used in this case to avoid the leakage.…”
In this paper, we have characterized an AlGaN/GaN High Electron Mobility Transistor (HEMT) with a short gate length (Lg ≈ 0.15μm). We have studied the effect of short gate length on the small signal parameters, linearity parameters and gm-gd ratio in GaN HEMT devices. To understand how scaling results in the variation of the above-mentioned parameters a comparative study with higher gate length devices on similar heterostructure is also presented here. We have scaled down the gate length but the barrier thickness(tbar) remained same which affects the aspect ratio (Lg/tbar) of the device and its inseparable consequences are the prominent short channel effects (SCEs) barring the optimum output performance of the device. These interesting phenomena were studied in detail and explored over a temperature range of -40 oC to 80 oC. To the best of our knowledge this paper explores temperature dependence of SCEs of GaN HEMT for the first time. With an approach to reduce the impact of SCEs a simulation study in Silvaco TCAD was carried out and it is observed that a recessed gate structure on conventional heterostructure successfully reduces SCEs and improves RF performance of the device. This work gives an overall view of gate length scaling on conventional AlGaN/GaN HEMTs.
“…GaN-based devices, such as GaN/AlGaN high electron mobility transistors (HEMT) and GaN diodes, have been widely used as power devices because of their high breakdown voltage [ 1 , 2 , 3 ] and operation frequency [ 4 , 5 , 6 ]. Although GaN devices have many advantages, they are still suffering from some problems such as short channel effect [ 7 , 8 , 9 ] and current collapse effect [ 10 , 11 , 12 ]. To solve these problems, some researchers proposed double channel GaN HEMTs [ 13 , 14 , 15 , 16 , 17 , 18 ], which contain two GaN/AlGaN heterojunction conductive channels.…”
A side ohmic contact mode for the double channel GaN/AlGaN epitaxial layer is proposed in this paper. Rectangle transmission line model (TLM) electrodes are prepared, and the specific contact resistance is tested at the annealing temperatures from 700 °C to 850 °C. The results show that the minimum specific contact resistance is 2.58 × 10−7 Ω·cm2 at the annealing temperature of 750 °C, which is three to four times lower than the surface contact mode. Scanning electron microscope (SEM), energy dispersive spectrometer (EDS), and atomic force microscope (AFM) were carried out for the analysis of the morphology, element composition, and the height fluctuation at the contact edge. With the increase in the annealing temperature, the specific contact resistance decreases due to the alloying of electrodes and the raised number of N vacancies. However, when the annealing temperature exceeds 800 °C, the state of the stress in the electrode films transforms from compressive stress to tensile stress. Besides, the volume expansion of metal electrode film and the increase in the roughness at the contact edge leads to the degradation of the side ohmic contact characteristics.
“…In recent times, scaling down of devices to keep up with Moore's law has become a very difficult task with the conventional silicon based complementary metal oxide semiconductor (CMOS) technology. The primary hurdle can be identified as the short channel effects (SCEs) associated with metal oxide semiconductor field effect transistors (MOSFET) [1][2][3][4][5][6] which degrades the performance of MOSFETs in the short channel regime. Moreover, high leakage current in MOSFETs 7,8 worsens the problem.…”
In this research work, we have varied several parameters of a carbon nanotube based tunneling field effect transistor (CNT-TFET) such as the dielectric constant of the gate insulator (j), channel length, oxide thickness, doping level, and the nature of doping to investigate how the performance of the CNT-TFET is affected. The performance analysis has been done based on the following performance criteria: Subthreshold swing (SS), threshold voltage (V T), and on-current to off-current ratio (I on /I off). In addition, we have also analyzed how linearity and distortion figures of merit such as second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3) are affected by parametric variation. By observing the impact of parametric variation on this large number of performance metrics, a compromise choice of structural parameters is possible depending on the application. Moreover, we have proposed an asymmetric doping design that suppresses the highly undesirable ambipolar behavior in CNT-TFET. In a real-space approach, the simulation study has been carried out using the elegant non-equilibrium Green's function (NEGF) formalism considering tight-binding Hamiltonian.
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