Suppression of Hot-Hole Injection in High-Voltage Triple RESURF LDMOS With Sandwich N-P-N Layer: Toward High-Performance and High-Reliability

Qiao, Ming; Yuan, Zhangyi’an; Yi, Li; Zhou, Xin; Jiang, Feng; Yang, Junfeng; Cai, Ying; Li, Zhaoji; Zhang, Bo

doi:10.1109/ispsd46842.2020.9170104

Cited by 12 publications

(3 citation statements)

References 15 publications

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“…( 1). The performance of proposed TOTR-LDMOS and some typical optimized LDMOS [11][12][13][14] are shown in Fig. 7 and summarized in Table 2.…”

Section: Breakdown Voltagementioning

confidence: 99%

See 1 more Smart Citation

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Xu¹,

He²,

Liang³

et al. 2021

Chinese Phys. B

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A novel terminal-optimized triple RESURF LDMOS (TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolar-CMOS-DMOS (BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage (BV) and electrostatic discharge (ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse (TLP) tests, direct current (DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance (R on,sp) of 6.99 Ω⋅mm2. Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

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“…( 1). The performance of proposed TOTR-LDMOS and some typical optimized LDMOS [11][12][13][14] are shown in Fig. 7 and summarized in Table 2.…”

Section: Breakdown Voltagementioning

confidence: 99%

“…BV (V) R on,sp (Ω•mm 2 ) DTI-DMOS [11] 758 9.62 LFCC-DMOS [12] 705 8.05 NPN-LDMOS [13] 535 3.24 JITR-LDMOS [14] 792 9.52 TOTR-LDMOS (this work) 817 6.99 450 500 550 600 650 700 750 800 850 900 950 2 BV (V) triple RESURF LDMOS limit [10] DTI LDMOS [11] LFCC LDMOS [12] NPN LDMOS [13] JITR LDMOS [14] TOTR LDMOS Fig. 7.…”

Section: Devicesmentioning

confidence: 99%

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Xu¹,

He²,

Liang³

et al. 2021

Chinese Phys. B

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show abstract

“…limit' relationship of R on,sp ∝ BV 2.5 , which leads to high power consumption, many methods have been proposed to improve the trade-off relationship between the R on,sp and BV [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. By introducing a P-type region into the N-drift, typical RESURF [6][7][8][9][10][11][12][13] and superjunction [14][15][16][17][18][19][20][21] technologies not only decrease the R on,sp by enhancing the depletion effect to increase the N-drift doping concentration (N d ), but also increase the BV by modulating the electric field distribution. However, the R on,sp of these methods is strongly dependent upon the N d , and charge imbalance will result in BV degradation.…”

Section: Introductionmentioning

confidence: 99%

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

Wei¹,

Dai²,

Ma³

et al. 2022

Semicond. Sci. Technol.

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To improve the tradeoff relationship between the specific on-resistance (Ron,sp) and breakdown voltage (BV), a novel lateral double-diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) with ingenious layout design is proposed and investigated by simulations and experiments. The proposed LDMOS features a specific convex-shape field plate (CFP) structure at source side and two separated integrated diodes (SID) at the drain side. On one hand, a continuous electron accumulation layer is formed from source to drain in the on-state, providing an ultralow current path to decrease the specific on-resistance (Ron,sp). On the other hand, the CFP and SID structures allow the proposed device to make full use of the drift length to sustain the off-state voltage, so that the novel device could maintain the same BV level with a shorten drift length. Thus, the proposed CFP-SID LDMOS achieves a much lower Ron,sp and better Ron,sp-BV tradeoff relationship. The experimental results illustrate that the CFP-SID LDMOS realizes a BV of 518V and Ron,sp of 23.5 mΩ·cm2 with a high figure of merit (FOM) of 11.42MW/cm2. Compared with the triple-RESURF LDMOS under the same BV, the proposed device decreases the Ron,sp by 53.8%.

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A Superjunction Extended Triple Gate LDMOS with Charge Accumulation Effect

He,

Chen,

Duan

2023

Silicon

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Suppression of Hot-Hole Injection in High-Voltage Triple RESURF LDMOS With Sandwich N-P-N Layer: Toward High-Performance and High-Reliability

Cited by 12 publications

References 15 publications

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Simulation and experimental study on a high figure of merit LDMOS with ingenious layout design

A Superjunction Extended Triple Gate LDMOS with Charge Accumulation Effect

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