Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering

Abstract

A novel asymmetric isolated gates dopant segregated Schottky barrier MOSFET (AIG DS-SBMOS) for the suppression of ambipolar leakage current (I AMB ) using gate engineering is reported. The AIG DS-SBMOS consists of a dopant segregated source/drain with two asymmetric isolated gates (control gate, fixed gate) having different metal work functions. The control gate is used to control current conduction by modifying the Schottky barrier height and width at the source/ channel junction; while, the fixed gate modulates the drain side Schottky barrier to the suppress I AMB caused by hole injection in the off-state condition. In contrast to the conventional SBMOS and DS-SBMOS that suffer from ambipolarity, the proposed device is free from severe I AMB . Moreover, the proposed AIG DS-SBMOS has a high I ON /I OFF ratio of 10 7 with nearly the same I ON and subthreshold swing as that of the DS-SBMOS. The proposed device structure is especially beneficial for nanowire-based transistors.Introduction: Below sub-45 nm technology node, conventional CMOS devices face various issues related to short-channel effects and increased source/drain (S/D) series resistance [1]. To overcome these issues, devices such as the Schottky barrier MOSFET (SBMOS) have been extensively studied in the last decade as a possible solution [2,3]. SBMOS devices offer inherent advantages such as immunity to shortchannel effects, low S/D series resistance and scalability up to sub-10 nm gate length dimensions [4]. However, they suffer from two major constraints as compared with their conventional counterparts, i.e. a low driving current (I ON ) and high I AMB due to ambipolar conduction [5]. To enhance the I ON of the device, a number of studies have been reported [6,7], although for the reduction of I AMB , considerable effort is still required. In a few published reports [8-10], this severe I AMB was suppressed by: (i) inserting an Si 3 N 4 layer between the S/D contactchannel interfaces, (ii) using a field-induced drain extension between the drain and channel interface, and (iii) employing a recessed channel architecture with asymmetric S/D contacts. However, none of these above-mentioned techniques are optimal for SBMOS design. The first and second methods lead to increased fabrication complexity and are difficult to adopt for nanoscale device implementations. In the third method, ambipolar conduction is not significantly suppressed and it requires asymmetric S/D contacts for on/off state performance enhancement. Thus, in this Letter, to effectively suppress the I AMB , we propose and investigate a novel asymmetric isolated gates dopant segregated (AIG DS)-SBMOS structure as an alternative. In the proposed device, we employed two asymmetric isolated gates (control gate and fixed gate) to control the carrier injection in the on-and the offstate condition. The control-gate modulates the source side barrier for current conduction in the on state. Moreover, the additional gate at the drain side, named as a fixed gate, effectively modifies the Schottky barr...

A physics‐based threshold voltage model for hetero‐dielectric dual material gate Schottky barrier MOSFET

“…However, SB‐MOSFET suffers from two major issues such as ambipolar effects, drive current capability and off‐state leakage current in SB‐MOSFET can be substantial in compared to single material gate SB‐MOSFET (conventional). So far, various device structures have been examined for further improvement in device performance; dual metal gate structures were proposed to improve the gate control over the channel and SCEs . The alternative method to enhance the I on current is to increase the pocket doping are applied in SB‐TFET .…”

“…The gate dielectric is confined in 2 nm thickness to attain better sensitivity in gate all around SB‐MOSFET. Furthermore, the advantages of dual metal gate SB‐MOSFET is advantages to reduce ambiploar current in single gate SB device . This paper is focusing on the modeling of hetero‐dielectric (high‐k [HfO 2 ] and low‐k [SiO 2 ]) dual material gate (HDDMG) SB‐MOSFET, where a simplified analytical model has been developed for surface potential, electric field, and threshold voltage with impact of hetero‐gate dielectric.…”

“…So far, various device structures have been examined for further improvement in device performance; dual metal gate structures were proposed to improve the gate control over the channel and SCEs. 14,15 The alternative method to enhance the I on current is to increase the pocket doping are applied in SB-TFET. 16 The SB-MOSFET with a full-depleted pocket doping in between the metal and lightly doped channel region is proposed to improve the tunneling of carrier is successfully fabricated.…”

“…Furthermore, the advantages of dual metal gate SB-MOSFET is advantages to reduce ambiploar current in single gate SB device. 15,16,24 This paper is focusing on the modeling of hetero-dielectric (high-k [HfO 2 ] and low-k [SiO 2 ]) dual material gate (HDDMG) SB-MOSFET, where a simplified analytical model has been developed for surface potential, electric field, and threshold voltage with impact of hetero-gate dielectric. The parabolic approximation method is used to solve the 2-D Poisson's equation with appropriate boundary conditions.…”

Analysis and Performance Study of III–V Schottky Barrier Double-Gate MOSFETs Using a 2-D Analytical Model

“…Opportunities for ambipolar leakage improvement are discussed in [22]. Lee and Shin [23] reported a performance assessment of III-V ultrathin-body SB MOSFETs for similar materials as in the following analysis, but primarily with a focus on ballistic transport and the density-ofstates (DOS) bottleneck, reported in [24] and [25].…”