Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms

Modica, Paolo; Biondi, Alessandro; Buttazzo, Giorgio; Patel, Anup

doi:10.1109/icit.2018.8352429

Cited by 29 publications

(17 citation statements)

References 10 publications

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“…Differently from the literature mentioned above, however, we rely on virtualisation support. A lightweight hypervisor, namely Jailhouse, allocates physical memory pages that map to non-overlapping cache [13], [40], [28]. In comparison, our work sets itself apart because: (i) we propose a technique to perform deterministic allocation of cache content to lower pessimism in estimating Worst-Case-Execution Time (WCET); (ii) we conduct an in-depth evaluation on the impact of the additional memory translation layer introduced by virtualisation; and (iii) we investigate the benefits of cache invalidation, software-, and hardware-driven prefetching.…”

Section: Related Workmentioning

confidence: 99%

“…If a page with color A is cached, its lines can never evict cache lines that belong to a page with color B, as long as B = A. This is the principle behind color-based cache partitioning that has been largely explored in the literature [28], [25], [34].…”

Section: B Multi-level Cachesmentioning

confidence: 99%

“…A cleaner approach consists in leveraging virtualization extensions [28], [12]. In this case, a hypervisor and hence a two-stage translation regime for VAs is activated.…”

Section: A Coloring Strategy For Strict Partitioningmentioning

confidence: 99%

See 2 more Smart Citations

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, highperformance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in highperformance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.

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Section: Related Workmentioning

confidence: 99%

Section: B Multi-level Cachesmentioning

confidence: 99%

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Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Kloda

Solieri

Mancuso

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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“…If a page with color C i is cached, its lines can never evict cache lines that belong to a page with color C j , as long as C i = C j . This principle is at the base of color-based cache partitioning [1], [7]- [9]. In the SoC under analysis, C = 16 and the PA bits that affect the color of a page are bits 12-15 -see Figure 3.…”

Section: A Background On Caches and Coloringmentioning

confidence: 99%

The Potential of Programmable Logic in the Middle: Cache Bleaching

Roozkhosh

Mancuso

2020

2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Consolidating hard real-time systems onto modern multi-core Systems-on-Chip (SoC) is an open challenge. The extensive sharing of hardware resources at the memory hierarchy raises important unpredictability concerns. The problem is exacerbated as more computationally demanding workload is expected to be handled with real-time guarantees in nextgeneration Cyber-Physical Systems (CPS). A large body of works has approached the problem by proposing novel hardware redesigns, and by proposing software-only solutions to mitigate performance interference.Strong from the observation that unpredictability arises from a lack of fine-grained control over the behavior of shared hardware components, we outline a promising new resource management approach. We demonstrate that it is possible to introduce Programmable Logic In-the-Middle (PLIM) between a traditional multi-core processor and main memory. This provides the unique capability of manipulating individual memory transactions. We propose a proof-of-concept system implementation of PLIM modules on a commercial multi-core SoC. The PLIM approach is then leveraged to solve long-standing issues with cache coloring. Thanks to PLIM, colored sparse addresses can be re-compacted in main memory. This is the base principle behind the technique we call Cache Bleaching. We evaluate our design on real applications and propose hypervisor-level adaptations to showcase the potential of the PLIM approach.

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“…• Isolation and timing predictability: A predictable virtualization needs to provide techniques to limit delays incurred accessing the underlying shared hardware platform. This include the support for algorithms for temporal isolation [3], cache isolation [4], [5], and memory bandwidth reservation for both CPU cores and hardware accelerators [6], [7]. Adopting these techniques is also beneficial for making the system more secure, protecting a critical application from potential cyber-attacks.…”

Section: Introductionmentioning

confidence: 99%

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms

et al. 2021

Self Cite

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This paper presents SPHERE, a project aimed at the realization of an integrated framework to abstract the hardware complexity of interconnected, modern system-on-chips (SoC) and simplify the management of their heterogeneous computational resources. The SPHERE framework leverages hypervisor technology to virtualize computational resources and isolate the behavior of different subsystems running on the same platform, while providing safety, security, and real-time communication mechanisms. The main challenges addressed by SPHERE are discussed in the paper along with a set of new technologies developed in the context of the project. They include isolation mechanisms for mixed-criticality applications, predictable I/O virtualization, the management of time-sensitive networks with heterogeneous traffic flows, and the management of field-programmable gate arrays (FPGA) to provide efficient implementations for cryptography modules, as well as hardware acceleration for deep neural networks. The SPHERE architecture is validated through an autonomous driving use-case.INDEX TERMS cyber-physical systems, embedded systems, real-time systems, hypervisor, FPGA.

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Supporting temporal and spatial isolation in a hypervisor for ARM multicore platforms

Cited by 29 publications

References 10 publications

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

The Potential of Programmable Logic in the Middle: Cache Bleaching

SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms

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