Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems

Abstract

One of the main predictability bottlenecks of modern multi-core embedded systems is contention for access to shared memory resources. Partitioning and software-driven allocation of memory resources is an effective strategy to mitigate contention in the memory hierarchy. Unfortunately, however, many of the strategies adopted so far can have unforeseen side-effects when practically implemented latest-generation, highperformance embedded platforms. Predictability is further jeopardized by cache eviction policies based on random replacement, targeting average performance instead of timing determinism. In this paper, we present a framework of software-based techniques to restore memory access determinism in highperformance embedded systems. Our approach leverages OStransparent and DMA-friendly cache coloring, in combination with an invalidation-driven allocation (IDA) technique. The proposed method allows protecting important cache blocks from (i) external eviction by tasks concurrently executing on different cores, and (ii) internal eviction by tasks running on the same core. A working implementation obtained by extending the Jailhouse partitioning hypervisor is presented and evaluated with a combination of synthetic and real benchmarks.

The Key Role of Memory in Next-Generation Embedded Systems for Military Applications

“…Coloring support The software mechanism proposed for the considered problem was implemented on top of the Jailhouse hypervisor [9] and Xilinx Zynq Ultra-Scale+. This approach has been successfully evaluated in a demanding real-time setup [16].…”

“…We advocate instead an easy-to-deploy, legacy-friendly hypervisor solution which additional enable seamless consolidation of single-core systems -cache coloring is placed below bare-metal applications and OSs. More precisely, we chose a novel extension [9], to the Jailhouse hypervisor [10], an open-source, minimal, partitioning hypervisor designed for real-time and/or safety-critical use cases. The solution has been developed in the context of the EU Horizon 2020 HERCULES research project [11], whose goal is to develop a system stack for a the next-generation, highperformance multi-core real-time systems.…”

Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms

“…The relevant hardware features described in this paper are to be considered to efficiently distribute tasks within the CPU complexes. We highlight that memory-centric scheduling often implies some sort of partitioning within DRAM banks or portions of shared caches [31], [32]. In order to minimize the overhead of such software mitigation approaches, we will investigate how novel, hardware-based mechanisms can be dynamically tuned for solving the memory contention bottleneck in heterogeneous embedded SoCs [33], [34], [35].…”

Schedulability Analysis of Global Scheduling for Multicore Systems With Shared Caches

“…There are two cache partitioning methods: software-based and hardware-based techniques [10]. The most common software-based cache partitioning technique is page coloring [11], [12], [13], [14]. By exploiting the virtual to physical page address translations present in virtual memory systems at OS-level, page addresses are mapped to predefined cache regions to avoid the overlap of cache spaces.…”