Support excitation scheme for transient analysis of JEDEC board-level drop test

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

“…The results revealed that the stress-buffer-enhanced package survived over 100 drops. Moreover, the failure occurred at the interconnection of the package which is markedly different from the failure mode at solder joint observed in the drop test experiments of conventional wafer level package (WLP) [6,7].…”

A review of board level solder joints for mobile applications

“…But since the drop-shock event is only moderately transient in nature, the implicit algorithm would in fact have been more computationally efficient. The use of an implicit algorithm for modelling drop-shock was demonstrated by Yeh and Lai [62] of ASE applying ''base excitation" method on the commercial ANSYS solver. The equation of motion is expressed as…”

Effects of different drop test conditions on board-level reliability of chip-scale packages

“…The transient finite element analysis for JEDEC boardlevel drop tests followed the support excitation scheme [18,19] incorporated with an implicit solver. To simplify the analysis, only the central package, U8, was modeled.…”

“…In order to understand structural responses and failure mechanisms of the board-level test vehicle subjected to JEDEC or other pulse-controlled drop test methodologies alike, numerous theoretical (e.g., [5][6][7][8]), experimental (e.g., [9][10][11][12][13]), and numerical studies (e.g., [13][14][15][16][17][18][19][20]) have been conducted. Most of these studies focused on a single test condition only.…”

“…The transient finite element analysis based on the support excitation scheme [18,19] was also performed to obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions.…”