Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

Abstract

In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below cm bit (no SEUs detected) at 500 mV supply voltage, cm bit at 250 mV supply voltage, and cm bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least , and (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between MeV-cm mg and MeV-cm mg. Index Terms-Complimentary metal-oxide semiconductor (CMOS), flip-flop, low power, low voltage, radiation tolerant, single event transient (SET), single event upset (SEU).

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

“…Fig. 4 shows its layout comprising an area of 25.35 μm 2 , where only M1 metal layer are used for routing the interconnects, so it does not affect the overall routing in VLSI automatic design.…”

“…A single event upset (SEU) is generated when the collected charge of the struck node is larger than the critical charge in a radiation particle strike, and probability of incurring an SEU is dramatically increasing in the sequential cells [1][2][3]. Thus, latches that are widely used to latch the key signals in the data propagation paths need to be protected to avoid the data corruption [4].…”

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

“…The basic sampling, keeper circuit, and C-element parts are used to implement the hybrid FF. From related works [25][26][27][28][29][30][31][32][33][34][35], authors have focused to discuss the SEE effects only, another solution is C-element, which is proposed in [35] to overcome the SEE effects such as SET, and SEU in hybrid FF design. The hybrid pulsed FF, using C-element as a fundamental stage, provides better result to resist switching activity and improves data activity.…”

“…Hasanbegovic , et al [34] investigated the efficiency of temporal and spatial hardening techniques in FF design with SEU mitigation. The SEU‐tolerant FF topologies intended for low supply voltage operation.…”

“…From related works, the sequential CMOS circuits are affected by SEU [26–28, 31, 34] and SET [28–30, 33]. The sources of these effects are introduced from radiation errors.…”