Superior Reliability of Gate-All-Around Polycrystalline Silicon Thin-Film Transistors with Vacuum Cavities Next to Gate Oxide Edges

Abstract

The electrical characteristics and reliability of n-type gate-all-around (GAA) polycrystalline silicon thin-film transistors (poly-Si TFTs) with vacuum cavities next to the gate oxide edges are investigated. This novel structure is successfully fabricated by spacer formation, partial wet etching of a gate oxide, and in situ vacuum encapsulation. The electrical characteristics of the GAA poly-Si TFTs with vacuum cavities are superior to those of traditional GAA poly-Si TFTs because the vacuum cavity serves as an offset region to decrease the leakage current in the OFF state and as a field-induced drain (FID) to sustain the on-current in the ON state. In addition, regardless of whether static or dynamic electrical stress is imposed on these devices, the GAA poly-Si TFTs with vacuum cavities exhibit superior reliability to traditional ones owing to the simultaneous reduction of vertical and lateral electric fields near the drain junction during bias stressing due to the greater equivalent gate oxide thickness on the gate electrode edges