SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

Seiculescu, Ciprian; Murali, Srinivasan; Benini, Luca; Micheli, Giovanni De

doi:10.1109/date.2009.5090625

Cited by 79 publications

(35 citation statements)

References 32 publications

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“…Besides, some works have focused on developing 3D NoC architectures [49] and as we have seen in section 3, NoC tools developers have also anticipated these advancements by proposing tools that are dedicated for 3D NoC design and simulation [30]. However, other studies proposed different approach by adding the NoC concept to the bus one and so, keeping some data transfer to classical buses.…”

Section: G Other Available Noc Toolsmentioning

confidence: 99%

“…The main feature added is the generation of specifications for the future 3D Wafers [30]. Both versions were developed by the team of Prof. Giovanni De Micheli, a pioneer of research for NoCs with many publications in the NoC subject like a particular article [4] with over 1900 citations (Google Scholar statistics) and several books on this subject [31].…”

Section: Sunfloor -3d Sunfloormentioning

confidence: 99%

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A Survey of Network-On-Chip Tools

Achballah¹,

Saoud²

2013

IJACSA

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Abstract-Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances, reliability and integration capacity. The last advantage has induced the growth of the number of cores or Intellectual Properties (IPs) in a same chip. Unfortunately, this important number of IPs has caused a new issue which is the intra-communication between the elements of a same chip. To resolve this problem, a new paradigm has been introduced which is the Network-On-Chip (NoC). Since the introduction of the NoC paradigm in the last decade, new methodologies and approaches have been presented by research community and many of them have been adopted by industrials. The literature contains many relevant studies and surveys discussing NoC proposals and contributions. However, few of them have discussed or proposed a comparative study of NoC tools. The objective of this work is to establish a reliable survey about available design, simulation or implementation NoC tools. We collected an important amount of information and characteristics about NoC dedicated tools that we will present throughout this survey. This study is built around a respectable amount of references and we hope it will help scientists.

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Section: G Other Available Noc Toolsmentioning

confidence: 99%

Section: Sunfloor -3d Sunfloormentioning

confidence: 99%

A Survey of Network-On-Chip Tools

Achballah¹,

Saoud²

2013

IJACSA

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“…Murali et al [15] propose a 3D NoC topology synthesis algorithm, which is an extension to their previous 2D work [19], described above. The 3D NoC synthesis problem has been shown to be NP-hard in [21].…”

Section: Contributions Of Our Workmentioning

confidence: 99%

Application-specific 3D Network-on-Chip design using simulated allocation

Zhou¹,

Yuh²,

Sapatnekar³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this paper, we consider the application-specific NoC architecture design problem in a 3D environment. We present an efficient floorplanaware 3D NoC synthesis algorithm, based on simulated allocation, a stochastic method for traffic flow routing, and accurate power and delay models for NoC components. We demonstrate that this method finds greatly improved topologies for various design objectives such as NoC power (average savings of 34%), network latency (average reduction of 35%) and chip temperature (average reduction of 20%).

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“…Recent research efforts have been addressing 3-D NoCs [27], [72], [112], [144]. Relevant problems are the modeling and management of the anisotropic delays, the physical design of the NoC with specific reference to floorplanning and global routing of the links through TSVs (with possible limitation on count, size, and positions), and the corresponding impact on NoC architectures.…”

Section: -D Integrationmentioning

confidence: 99%

An Outlook on Design Technologies for Future Integrated Systems

Micheli

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The economic and social demand for ubiquitous and multifaceted electronic systems-in combination with the unprecedented opportunities provided by the integration of various manufacturing technologies-is paving the way to a new class of heterogeneous integrated systems, with increased performance and connectedness and providing us with gateways to the living world. This paper surveys design requirements and solutions for heterogeneous systems and addresses design technologies for realizing them.

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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

Cited by 79 publications

References 32 publications

A Survey of Network-On-Chip Tools

A Survey of Network-On-Chip Tools

Application-specific 3D Network-on-Chip design using simulated allocation

An Outlook on Design Technologies for Future Integrated Systems

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