Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms

HajiRassouliha, Amir; Taberner, Andrew J.; Nash, Martyn P.; Nielsen, Poul M. F.

doi:10.1016/j.image.2018.07.007

Cited by 91 publications

(57 citation statements)

References 75 publications

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“…However, based on the past lines of work, we will mainly focus on the NVIDIA GPU families since they are the most popular hardware platform used in the CGH and image processing community. 53…”

Section: Graphics Processing Unitsmentioning

confidence: 99%

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Hardware implementations of computer-generated holography: a review

et al. 2020

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Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations.

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Section: Graphics Processing Unitsmentioning

confidence: 99%

“…The toolchain support is considered mature and time-proven, further minimizing the development time and difficulty. 53…”

Section: Digital Signal Processorsmentioning

confidence: 99%

Hardware implementations of computer-generated holography: a review

et al. 2020

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“…The latter are typically needed to implement time-and/or energy-critical operations, which represent an overhead for the application. This allows energy efficiencies higher than traditional GPUs to be achieved [25]. In the literature, several FPGA-based designs have been presented to accelerate the inference of 16- [26][27][28][29] and 8-bit [30,31] fixed-point quantized CNNs.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

Spagnolo

Perri

Frustaci

et al. 2019

JLPEA

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Due to the huge requirements in terms of both computational and memory capabilities, implementing energy-efficient and high-performance Convolutional Neural Networks (CNNs) by exploiting embedded systems still represents a major challenge for hardware designers. This paper presents the complete design of a heterogeneous embedded system realized by using a Field-Programmable Gate Array Systems-on-Chip (SoC) and suitable to accelerate the inference of Convolutional Neural Networks in power-constrained environments, such as those related to IoT applications. The proposed architecture is validated through its exploitation in large-scale CNNs on low-cost devices. The prototype realized on a Zynq XC7Z045 device achieves a power efficiency up to 135 Gops/W. When the VGG-16 model is inferred, a frame rate up to 11.8 fps is reached.

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“…They exploit parallelism by means of either multi-core processors and Graphics Processing Units (GPUs) [5,[27][28][29][30][31] or custom hardware architectures [10,11,[14][15][16][17][18][19][20][21][22][23]26]. As it is well known, for many consumer applications, like those related to the Internet of things (IoT), reaching high speed is as important as achieving low cost and high energy efficiency [16,32]. The design discussed in this paper is tailored to such a class of applications.…”

mentioning

confidence: 99%

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

2020

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Connected component labeling is one of the most important processes for image analysis, image understanding, pattern recognition, and computer vision. It performs inherently sequential operations to scan a binary input image and to assign a unique label to all pixels of each object. This paper presents a novel hardware-oriented labeling approach able to process input pixels in parallel, thus speeding up the labeling task with respect to state-of-the-art competitors. For purposes of comparison with existing designs, several hardware implementations are characterized for different image sizes and realization platforms. The obtained results demonstrate that frame rates and resource efficiency significantly higher than existing counterparts are achieved. The proposed hardware architecture is purposely designed to comply with the fourth generation of the advanced extensible interface (AXI4) protocol and to store intermediate and final outputs within an off-chip memory. Therefore, it can be directly integrated as a custom accelerator in virtually any modern heterogeneous embedded system-on-chip (SoC). As an example, when integrated within the Xilinx Zynq-7000 X C7Z020 SoC, the novel design processes more than 1.9 pixels per clock cycle, thus furnishing more than 30 2k × 2k labeled frames per second by using 3688 Look-Up Tables (LUTs), 1415 Flip Flops (FFs), and 10 kb of on-chip memory.

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Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms

Cited by 91 publications

References 75 publications

Hardware implementations of computer-generated holography: a review

Hardware implementations of computer-generated holography: a review

Energy-Efficient Architecture for CNNs Inference on Heterogeneous FPGA

A Parallel Connected Component Labeling Architecture for Heterogeneous Systems-on-Chip

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