No abstract

Computer-generated holography (CGH) is a technique to generate holographic interference patterns. One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process. Previous publications targeting hardware platforms lack performance comparisons between different architectures and do not provide enough information for the evaluation of the suitability of recent hardware platforms for CGH algorithms. We aim to address these limitations and present a comprehensive review of CGH-related hardware implementations.

Traditional search algorithms for computer hologram generation such as Direct Search and Simulated Annealing offer some of the best hologram qualities at convergence when compared to rival approaches. Their slow generation times and high processing power requirements mean, however, that they see little use in performance critical applications. This paper presents the novel Sorted Pixel Selection (SPS) modification for Holographic Search Algorithms (HSAs) that offers Mean Square Error (MSE) reductions in the range of 14.7 − 19.2% for the test images used. SPS operates by substituting a weighted search selection procedure for traditional random pixel selection processes. While small, the improvements seen are observed consistently across a wide range of test cases and require limited overhead for implementation.

The generation of computer-generated holograms (CGH) require a significant amount of computational power. To accelerate the process, highly parallel field-programmable gate arrays (FPGA) are deemed to be a promising computing platform to implement non-iterative hologram generation algorithms. In this paper, we present a cost-optimized heterogeneous FPGA architecture based on one-step phase retrieval (OSPR) algorithm for CGH generation. The results indicate that our hardware implementation is 2.5× faster than the equivalent software implementation on a personal computer with a high-end multi-core CPU. Trade-offs between cost and performance have been demonstrated, and we have shown that the proposed heterogeneous architecture can be used in a compact display system that is cost-and size-optimized.

We combine a continuous feedback hardware-in-the-loop approach with a binary-phase SLM and an imaging sensor to produce a computer-generated holography system which is scalable in cost, tolerant to real-world effect and suitable for mass-market adoption.