Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

Sekiguchi, Shohei; Ahn, Minwook; Mizutani, Tomoko; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

doi:10.1109/jeds.2021.3108854

Cited by 6 publications

(4 citation statements)

References 12 publications

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“…3b. It is surprising that SS does not show a clear saturation and decreases from 62 mV/dec at 300 K to 4.2 mV/dec at 5.5 K measured in the range from I d = 0.01 to 10 nA/μm, different from previously reported devices [7], [9], [20], [21]. To characterize the real switch performance of transistors including the impact of the transition region at Cryo-T, we propose an effective average subthreshold swing SS th = (V th − V of f )/(log I th −log I of f ) where V off is the offvoltage, I off the off-current and I th corresponds to the current at V th as indicated in Fig.…”

Section: Resultscontrasting

confidence: 99%

“…2kT is the poly-Si depletion capacitance, ε Si is the dielectric constant of poly-Si, N p the doping concentration in poly-Si. At cryogenic 4b), the saturation current (V d = −1.2 V) increases dramatically from 13.6 μA/μm at RT to 81.2 μA/μm at 5.5 K. Benchmarking with reported stateof-the-art FETs [6], [7], [20]- [22], [26], [28]- [37], this work demonstrates the lowest SS, the smallest DIBL, the lowest SS th and a high G m at Cryo-T (Fig. 5).…”

Section: Resultsmentioning

confidence: 99%

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Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Han¹,

Sun²,

Richstein

et al. 2022

IEEE Electron Device Lett.

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Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SS th of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G m at 5.5 K.

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Section: Resultscontrasting

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Han¹,

Sun²,

Richstein

et al. 2022

IEEE Electron Device Lett.

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“…The thickness of the oxide is taken as 1 nm. In the above-said architectures, a lightly doped channel is employed with 1×10 16 cm -3 doping concentration and an increased doping concentration of 5×10 19 cm -3 is employed in the channel to introduce halo doping at the end of the source side with implantation method in the fabrication process for adopting channel engineering [25]- [27]. A fixed halo length of 1.5 nm is used in the overall channel length of 10 nm.…”

Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

Kumar

Balaji

Rao

2023

IJECE

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In this paper, we propose a low-k source side asymmetrical spacer halo-doped nanowire metal oxide semiconductor field effect transistor (MOSFET) design and analysis. High-k spacer materials are now being researched extensively for improving electrostatic control and suppressing short-channel effects in nanoscaled electronics. However, the high-k spacers' excessive increase in fringe capacitance degrades the dynamic circuit performance. Surprisingly, this approach achieves a significant reduction in gate capacitance by maximizing the use of high-k spacer material. Three different structures, symmetrical dual-k spacer, low-k drain side asymmetrical spacer, low-k source side asymmetrical spacer halo doped nanowire MOSFET architectures are simulated and among them low-k source side asymmetrical spacer halo doped nanowire MOSFET architecture giving lower gate capacitance. After doing 3D simulations in Silvaco technology computer-aided design (TCAD) we observed that the gate capacitance and intrinsic delay are 1.23x10<sup>-17</sup> farads and 1.11x10<sup>-12</sup> seconds respectively for low-k source side asymmetrical spacer architecture and these are less as compared to high-k spacer architecture. So, the proposed structure is highly recommended for digital applications.

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“…* Authors to whom any correspondence should be addressed. [1][2][3] and GaAs/InP [4,5] have been intensively studied as the readout/control circuits and low-noise amplifiers. Apart from these traditional devices, wide bandgap semiconductor GaNbased high-electron-mobility transistors (HEMTs) recently have emerged as a promising candidate for the cryo-systems thanks to their superior material and device properties [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

Zeng¹,

Zhang²,

Luo³

et al. 2022

J. Phys. D: Appl. Phys.

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In this work, the device characteristics of GaN-based high-electron-mobility transistors (HEMTs) were systematically investigated by the direct current (DC) and low-frequency noise (LFN) measurements within the temperature ranging from 300 K to 4.2 K. The temperature-dependent behavior of the on- and off-state electrical properties was statistically analyzed, highlighting an overall improved device performance under the cryogenic temperatures. In addition, the LFN of the device exhibited an evident behavior of 1/f noise from 10 Hz to 10 kHz in the measured temperature range and can be well described by the carrier number fluctuations with correlated mobility fluctuations (CNF/CMF) model down to 4.2 K. Based on this model, we further extracted and discussed the defect-related behavior in the devices under low-temperature environments. These experimental results provide insights into the device characteristics of GaN-based HEMTs under cryogenic environments, motivating further studies into the GaN-based cryo-devices and systems.

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Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

Cited by 6 publications

References 12 publications

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

DC and low-frequency noise characteristics of GaN-based HEMTs under cryogenic temperatures

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