Subthreshold-current reduction circuits for multi-gigabit DRAM's

Sakata,; Horiguchi,; Itoh,

doi:10.1109/vlsic.1993.920532

Cited by 34 publications

(8 citation statements)

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“…For high performance, the degenerating resistor is bypassed to ground, but during the standby state, the resistor is used to bias the source terminal of the off device. Another variation known as self-reverse biasing [Kawahara et al 1993;Sakata et al 1994] replaces the switched source impedance with another off transistor so that the equilibrium value is set through a series of "off devices." This technique was first applied to decoded word line driver circuits where the large drivers can have large leakage currents.…”

Section: Leakage Power Reductionmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

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Section: Leakage Power Reductionmentioning

confidence: 99%

Challenges and design choices in nanoscale CMOS

Narendra

2005

J. Emerg. Technol. Comput. Syst.

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“…There are a number of techniques in the literature to help counter the effects of higher subthreshold leakage. Their application to low-power/high-performance products is promising [8][9][10]15].…”

Section: Design Responsementioning

confidence: 99%

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

et al. 1995

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An experimental 2.0*volt low-power PowerPC 601™ Microprocessor built In a modified 3.6-volt, 0.6-tim IBiUI CMOS technology Is described. By using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power marlcet while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O Interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. The paper reviews the motivation behind lowpower microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction. IntroductionThe use of fully capable microprocessors in portable consumer electronics represents one of the fastest-growing segments of the electronics market. These applications include computing (tablet, laptop, and notebook computers), entertainment (gameboys, virtual reality toys), and communications (cellular phones, wireless modems). By one estimate [1], the subnotebook computer market alone will grow at a 91% compound annual growth rate through 1997, easily exceeding growth rates of the workstation and deskside/desktop segments.

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“…Similar approaches have been applied to caches [12][13] and to DRAMs [14]. The Boosted Gate MOS (BGMOS) approach [15] and Super Cut-off CMOS (SCCMOS) [16] both enhance performance by respectively overdriving the sleep device in active mode and underdriving in standby mode.…”

Section: Introductionmentioning

confidence: 99%

Design methodology for fine-grained leakage control in MTCMOS

Calhoun

Honoré

Chandrakasan

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 m, dual V T testchip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8X measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active CLBs by up to 2.2X (measured) for some CLB configurations.

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Subthreshold-current reduction circuits for multi-gigabit DRAM's

Cited by 34 publications

References 0 publications

Challenges and design choices in nanoscale CMOS

Challenges and design choices in nanoscale CMOS

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Design methodology for fine-grained leakage control in MTCMOS

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