Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Abstract

An experimental 2.0*volt low-power PowerPC 601™ Microprocessor built In a modified 3.6-volt, 0.6-tim IBiUI CMOS technology Is described. By using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power marlcet while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O Interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. The paper reviews the motivation behind lowpower microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction. IntroductionThe use of fully capable microprocessors in portable consumer electronics represents one of the fastest-growing segments of the electronics market. These applications include computing (tablet, laptop, and notebook computers), entertainment (gameboys, virtual reality toys), and communications (cellular phones, wireless modems). By one estimate [1], the subnotebook computer market alone will grow at a 91% compound annual growth rate through 1997, easily exceeding growth rates of the workstation and deskside/desktop segments.