Sub-threshold standard cell library design for ultra-low power biomedical applications

Li, Mingzhong; Leong, C.K.; Law, Man‐Kay; Mak, Pui-In; Vai, Mang-I; Martins, Rui P.

doi:10.1109/embc.2013.6609785

Cited by 16 publications

(4 citation statements)

References 7 publications

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“…To begin with the front-end design stage, firstly, the schematic of all standard cells in the library are designed from transistor level. After that, symbol creation and do simulation at corners [16]. Next, in the back-end design stage, to optimize the layout design in term of area and routing, the layout design needs to have some rules as follows:…”

Section: Standard Cell Library Designmentioning

confidence: 99%

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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In this paper, a novel approach to design a Process Design Kit Digital for CMOS 180nm process is presented. This work proposes a detailed flow to design a PDK Digital using Ocean language, which is a vital element in the semi-custom design and applied in education purposes in universities in Vietnam. The PDK digital includes Standard Cell Library containing 47 standard cells and Wire-Load Model. The library is designed based on the CMOS 180nm process with a supply voltage of 1.8V.

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Section: Standard Cell Library Designmentioning

confidence: 99%

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Cong¹,

Le-Thanh²,

Bao³

et al. 2021

Adv. sci. technol. eng. syst. j.

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“…In light of this context, current research trends are leaning toward designing analog blocks using digital standard cells [27]. This approach can either emulate the behavior of analog building blocks or implement analog functions within the digital domain [28].…”

Section: Introductionmentioning

confidence: 99%

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

Sala,

Centurelli,

Scotti

et al. 2024

IEEE Access

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In this paper a novel ultra-low voltage (ULV) standard-cell-based comparator which provides rail-to-rail input common-mode range (ICMR) is presented. The topology, unlike the others in the literature, uses only 2-inputs NAND gates and is able to operate with supply voltages as low as 0.15V. A detailed theoretical analysis based on transistor level modeling is provided to explain the operating principle and highlight the performance advantages of the proposed comparator. The circuit has been tested through several simulations, including corner analysis and Monte Carlo runs, by using three different technologies: 180 nm, 130 nm and 28 nm for both a supply voltage of 0.3 V and 0.15 V. The results found not only confirm the robustness of the proposed comparator, but also demonstrate very advantageous performances. Indeed, for the same technology node it exhibits the highest speed and the lowest EDP (about ten times lower than the one of the others standard-cell-based comparators in the literature). It exhibits also the lowest power consumption and silicon area.

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“…Full custom and semi-custom IC implementation approaches have been adopted to meet these challenges. [2][3][4] In full custom design, everything is created manually. Each transistor and wire in a layout design can be set up as wanted, optimized for di®erent performance metrics.…”

Section: Introductionmentioning

confidence: 99%

“…A sub-threshold standard cell library is generated by using a standard 0.18 m CMOS technology node. 2 Logic cells are generated through schematic design, transistor width scaling and layout design. The characterizations of cells are based on timing, power and functionality.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

Sharma

Pattanaik

2016

J CIRCUIT SYST COMP

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In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and bu®er logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8 V by using Silvaco's EDA tools. All generated cells have same cell height of 1.58 m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS'85 benchmark circuits 74181 and c17 are designed and veri¯ed with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.

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Sub-threshold standard cell library design for ultra-low power biomedical applications

Cited by 16 publications

References 7 publications

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

A Novel Approach to Design a Process Design Kit Digital for CMOS 180nm Technology

Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

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