Abstract:In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and bu®er logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8 V by using Silvaco's EDA tools. All generated cells have same cell height of 1.58 m. The proposed… Show more
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