Sub-100 nm silicon on insulator complimentary metal–oxide semiconductor transistors by deep ultraviolet optical lithography

Abstract

Articles you may be interested inFabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning technique Sub-30 -nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics

Polymeric sidewall transfer lithography

“…The fabrication of nano-scale patterns has become a critical issue due to the increasing need to shrink devices in integrated circuits in order to improve the device performance and reduce power consumption. To achieve this goal, many advanced techniques have been employed such as deep ultraviolet lithography (DUV) [1], extreme ultraviolet lithography (EUV) [2], and E-beam lithography [3]. Although these novel techniques are able to create ultra-small structures, their high-cost process makes these techniques not commonly accessible.…”

Πολυμερικά Υλικά Και Διεργασίες Για Μικρολιθογραφία Σε Λεπτά Υμένια

“…Γενικά, ο κανόνας που έχει ισχύσει µέχρι σήµερα είναι ότι για ορισµένο µήκος κύµατος µπορούν να τυπωθούν δοµές διάστασης περίπου ίσης µε αυτό. Η εισαγωγή των RET αυξάνει σηµαντικά την ανάλυση, µέσω της µείωσης του παράγοντα k 1 , και έχει δειχθεί ότι είναι δυνατή η απεικόνιση δοµών της τάξης του λ/6 ή ακόµα και λ/10 όπου λ=248 nm [82][83]…”