Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, N.; Ogura, Atsushi; Narihiro, M.; Arai, K.; Ochiai, Yukinori; Takeuchi, Kiyoshi; Yamamoto, Tetsuya; Mogami, T.

doi:10.1109/iedm.2003.1269446

Cited by 62 publications

(47 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The oxide thickness is fixed at 1 nm for all structures [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…Compared with the single-gate (SG) SOI, these structures suppress short channel effects (SCEs), and have high transconductance and ideal subthreshold swing. They have a superior ability in channel control, so the drain induced channel barrier height lowing (DIBL), threshold voltage (V th ) roll off, and off state leakage is greatly suppressed [1][2][3][4][5][6][7]. The structure can be subject to further optimization to sustain more structural benefit.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Li¹,

Lee²,

Chou

2004

Simulation of Semiconductor Processes and Devices 2004

View full text Add to dashboard Cite

In this paper, electrical characteristics of nanoscale single-, double-, and all-around-gate silicon-0n-insulator (SOI) devices are computational investigated by using a quantum mechanical simulation. Considering several important properties, such as on/off current ratio, drain induced channel barrier height lowering, threshold voltage roll off, and subthreshold swing, geometry aspect ratio is systematically calculated and characterized among structures. To obtain good operation characteristics, the ratio of channel length and silicon film thickness should be optimized with respect to device structures.

show abstract

“…The oxide thickness is fixed at 1 nm for all structures [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Li¹,

Lee²,

Chou

2004

Simulation of Semiconductor Processes and Devices 2004

View full text Add to dashboard Cite

show abstract

“…This decreasing scale allows in principle to include more transistors on a chip thereby enabling larger, faster, cheaper circuits to be built -widely captured through Moore's law [2]. However, it is now accepted that previous assumptions on the uniformity of transistor devices no longer hold true [3][4][5][6][7]. The atomic dimensions of transistor devices introduce variability caused by the microscopic (atomistic) differences of the transistors including for example the number and positioning of dopants in the silicon.…”

Section: Introductionmentioning

confidence: 99%

Secure, Performance-Oriented Data Management for nanoCMOS Electronics

Sinnott

Bayliss

Davenhall

et al. 2008

2008 IEEE Fourth International Conference on eScience

View full text Add to dashboard Cite

The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics (nanoCMOS) is focused upon delivering a production level e-Infrastructure to meet the challenges facing the semiconductor industry in dealing with the next generation of 'atomic-scale' transistor devices. This scale means that previous assumptions on the uniformity of transistor devices in electronics circuit and systems design are no longer valid, and the industry as a whole must deal with variability throughout the design process. Infrastructures to tackle this problem must provide seamless access to very large HPC resources for computationally expensive simulation of statistic ensembles of microscopically varying physical devices, and manage the many hundreds of thousands of files and meta-data associated with these simulations. A key challenge in undertaking this is in protecting the intellectual property associated with the data, simulations and design process as a whole. In this paper we present the nanoCMOS infrastructure and outline an evaluation undertaken on the Storage Resource Broker (SRB) and the Andrew File System (AFS) considering in particular the extent that they meet the performance and security requirements of the nanoCMOS domain. We also describe how metadata management is supported and linked to simulations and results in a scalable and secure manner.

show abstract

“…The device whose gate length is below 50nm begins to appear in a market, and the operation of 5nm gate length device was presented in IEDM 2003 [1]. However, it will be very difficult to maintain the performance enhancement by scaling as it has been in the past.…”

Section: Introductionmentioning

confidence: 99%

CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation

Tanabe

Ashizawa

Oka

2004

Simulation of Semiconductor Processes and Devices 2004

View full text Add to dashboard Cite

In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using Mixed-mode option. The benefit of circuit delay in scaling will be maintained by introducing new structure (SOI, multi-gate), material (silicide, metal gate) and strain effect. However, concerning with SRAM SNM, it becomes already difficult to operate even in 65nm node.

show abstract

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Cited by 62 publications

References 2 publications

Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Comparison of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors

Secure, Performance-Oriented Data Management for nanoCMOS Electronics

CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation

Contact Info

Product

Resources

About