In this paper, electrical characteristics of nanoscale single-, double-, and all-around-gate silicon-0n-insulator (SOI) devices are computational investigated by using a quantum mechanical simulation. Considering several important properties, such as on/off current ratio, drain induced channel barrier height lowering, threshold voltage roll off, and subthreshold swing, geometry aspect ratio is systematically calculated and characterized among structures. To obtain good operation characteristics, the ratio of channel length and silicon film thickness should be optimized with respect to device structures.