CMOS Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode Device Simulation

Abstract

In this paper, the circuit performances such as circuit delay, RF characteristics and SRAM static noise margin are presented. These analyses are performed by threedimensional device simulation using Mixed-mode option. The benefit of circuit delay in scaling will be maintained by introducing new structure (SOI, multi-gate), material (silicide, metal gate) and strain effect. However, concerning with SRAM SNM, it becomes already difficult to operate even in 65nm node.

Discrete-Dopant-Fluctuated Transient Behavior and Variability Suppression in 16-nm-Gate Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

“…Diverse approaches have recently been proposed to study fluctuation-related issues in semiconductor devices [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30] and circuit. [31][32][33][34][35][36] However, little attention has been focused on the existence of transient characteristic fluctuations in the active devices due to random dopant placement. Moreover, due to the randomness of dopant position in the devices, the fluctuation of device gate capacitance is nonlinear and difficult to model with the current compact models.…”