Sub-10 nm Carbon Nanotube Transistor

Abstract

Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/μm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.

Carbon nanomaterials for electronics, optoelectronics, photovoltaics, and sensing

“…1c). 112 Progress in CNT electronics has moved beyond individual transistors. In particular, a complementary metal-oxide-semiconductor (CMOS) architecture is desired for energy efficient circuits.…”

Does water dope carbon nanotubes?

“…1,7,8 Optimal performance of these devices often requires the CNTs to have a particular electronic character, whether semiconducting or metallic, which is determined by the CNT chirality. The control of chirality during CNT synthesis is challenging, which has led to the development of alternative in-solution techniques for separating bulk-grown CNT samples with respect to electronic type.…”

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“…4 While serious integration challenges remain, recent successes with gate-all-around geometries and sub-10 nm channel lengths are extremely encouraging. [5][6][7] Although the progress is impressive, the remaining technological barriers and process variation, including difficulty in assembling CNTs with a controlled pitch, imperfect semiconducting purity, on-state current (I on ) variation, threshold voltage (V t ) variation, 8 and contact resistance, 9 still limit the performance. For practical applications in integrated circuits, each transistor must contain multiple CNTs in parallel in order to drive enough on-state current for high-speed switching as illustrated in Fig.…”