2019
DOI: 10.1109/led.2018.2885846
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Study on 4H-SiC GGNMOS Based ESD Protection Circuit With Low Trigger Voltage Using Gate-Body Floating Technique for 70-V Applications

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Cited by 25 publications
(12 citation statements)
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“…Consequently, several engineers select the SCR and LIGBT as high-voltage ESD protection devices, and various studies have been conducted to optimize their electrical characteristics [15]- [17]. However, because the critical electric field (E C ) is significantly high compared to the forward voltage drop in 4H-SiC, a strong snapback phenomenon occurs [18], [19]. In this snapback phenomenon, the difference between the trigger and holding voltages becomes larger than when silicon is used for fabrication.…”
Section: Introductionmentioning
confidence: 99%
“…Consequently, several engineers select the SCR and LIGBT as high-voltage ESD protection devices, and various studies have been conducted to optimize their electrical characteristics [15]- [17]. However, because the critical electric field (E C ) is significantly high compared to the forward voltage drop in 4H-SiC, a strong snapback phenomenon occurs [18], [19]. In this snapback phenomenon, the difference between the trigger and holding voltages becomes larger than when silicon is used for fabrication.…”
Section: Introductionmentioning
confidence: 99%
“…With the miniaturization of semiconductor feature size and the advancement of integrated circuits, catastrophic ElectroStatic Discharge (ESD) events can seriously deteriorate chip reliability [1][2][3][4][5][6]. Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10]. By contrast, silicon controlled rectifiers (SCRs) have been widely used due to their highest robustness per unit area [11][12][13][14][15][16][17][18][19][20].…”
Section: Introductionmentioning
confidence: 99%
“…By providing an additional ESD discharge path, the recently proposed low-dynamic -resistance-dual SCR (LDRDSCR) [5] has an excellent dynamic resistance. However, its low holding voltage falls outside the high-voltage ESD design window, and the device structure must be lengthened, increasing its on-resistance [8][9][10]. Fig.…”
Section: Introductionmentioning
confidence: 99%