4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

Do, Kyoung-Il; Jin, Seung-hoo; Lee, Byung-Seok; Koo, Yong-Seo

doi:10.1109/jeds.2021.3121212

Cited by 12 publications

(5 citation statements)

References 28 publications

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“…The turned‐on NPN parasitic bipolar transistor supplies a base current to the PNP1 and PNP2, and both the PNP transistor and one NPN transistor are turned on. As a result, the proposed ESD protection circuit has a high holding voltage because of its low positive feedback current gain [4, 5].…”

Section: Proposed Esd Protection Circuit Using Penta‐well Structurementioning

confidence: 99%

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Kwon

Koo

2022

Electronics Letters

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Various levels of circuits and systems in the ultra-low nanometer fabrication process should be considered to implement a system-on-chip (SOC) application to reduce power consumption. This letter is intended to propose a current detection structure that supplies and discharges additional current along the load current to provide the optimized voltage and power for SOC applications. The proposed electrostatic discharge (ESD) protection circuit placed on the power line and I/O has improved the reliability by preventing the direct or indirect destruction of the internal integrated circuit (IC) due to ESD. In addition, the proposed low drop out (LDO) regulator for the low-voltage applications has combined an ESD protection circuit to secure the high reliability of the IC. The proposed LDO regulator is implemented with a 0.18-μm BCD process and is kept an undershoot voltage of 23 mV and an overshoot voltage of 25 mV for a load current of 200 mA.

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Section: Proposed Esd Protection Circuit Using Penta‐well Structurementioning

confidence: 99%

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Kwon

Koo

2022

Electronics Letters

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“…而基于CMOS和Bipolar-CMOS-DMOS (BCD) 工艺制造的各种典型 SCR的温度依赖性分别被介绍和研究 [16,17] . 通过改进SCR结构, 可实现ESD触发电压和维持电压在高温环境中的稳定性 [18,19] . Do等 [20] 为了满足ESD 设计窗口研究了浮动技术减小4H-SiC GGNMOS的触发电压, 并进行了高温评估.…”

Section: -225℃的宽温度范围内的触发电压及维持电unclassified

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Li¹,

Cai²,

Zeng³

et al. 2022

Acta Phys. Sin.

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The holding voltage of electrostatic discharge (ESD) protective structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters exposes the protecting device to latch-up risk in high ambient temperature. In this paper, the holding characteristics of the ESD protection device under various ambient temperatures ranging from 30 to 195℃℃ are studied. The investigated ESD structure is the NMOS transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator (PDSOI) process. The ESD characteristics of the device are measured by the transmission line pulse (TLP) test system at different ambient temperatures. The test results show that the holding voltage (VH) decreases with the increasing temperature. TCAD simulation is carried out to support and analyze the experiment results, and the same trend of VH versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on VH and holding current (IH) are discussed in detail. When the Drain is subject to the same current pulsing, Source and Body is grounded, the distributions of current density, electric potential, and injected electron density of NMOS under various temperatures are extracted and analyzed. When the Drain, Source, and Body are grounded, the distributions of the electrostatic field under various temperatures are extracted and analyzed. The distributions of electric potential in NMOS indicate that voltage drop on the Drain-Body junction (VDB) is affected by ambient temperature significantly, and the variation of VDB dominates the variation trend of VH with increasing temperature. The decreasing electrostatic field and increasing injected electron density with decreasing temperature contribute to the decreasing VDB. The trend of IH and parasitic Body resistance (RBody) weakens the temperature dependence of the VH. The current gain of parasitic bipolar transistor (β) decreases with growing ambient temperature, which is the main contributor to the decreasing IH. Therefore, increasing IH and RBody is helpful to reduce the temperature dependence of the latch-immune ESD protection structure.

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“…First, the proposed LDO regulator exhibited excellent transient response characteristics and very low bias current characteristics even under high load current conditions. Second, the proposed LDO regulator is proven to meet the ESD requirements of low-voltage integrated circuits by integrating a SCR based ESD protection circuit to prevent IC damage due to static electricity [20]- [23].…”

Section: Introductionmentioning

confidence: 99%

Design of High-Robustness LDO Regulator With Floating SCR Based ESD Protection Circuit Using High Gain Buffer

Kwon,

Do,

Lee

et al. 2024

IEEE Access

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Currently, in the semiconductor market, reliability response to Electro Static Discharge (ESD) situations is being discussed as an alternative to internal Integrated Circuit (IC) destruction. In this paper, the ESD protection circuit design integrated into the Low Drop Out (LDO) regulator presents an alternative to the reliability of the internal IC. Additionally, the LDO regulator proposed in this paper is designed to minimize output voltage changes by significantly improving gain using a high gain buffer structure. Undershoot and overshoot were effectively regulated by utilizing a high gain buffer. Under the conditions of an input voltage range of 3.3-4.5 V, a maximum load current of 400 mA, and an output voltage of 3 V, the output of the proposed LDO regulator with a high gain buffer structure kept at the undershoot and overshoot voltages of 32 mV and 36 mV, respectively. In addition, the ESD protection circuit used so far was designed with only a single diode, but the proposed ESD protection circuit is a new structure designed based on Silicon Controlled Rectifier (SCR). The proposed ESD protection circuit has an incomparable area efficiency compared to diodes.INDEX TERMS LDO regulator, High reliability, ESD protection circuit, SCR, LDO regulator in integrated with ESD protection circuit.

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4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

Cited by 12 publications

References 28 publications

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

Design of High-Robustness LDO Regulator With Floating SCR Based ESD Protection Circuit Using High Gain Buffer

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