Study of Discrete Doping-Induced Variability in Junctionless Nanowire MOSFETs Using Dissipative Quantum Transport Simulations

Aldegunde, Manuel; Martı́nez, Antonio; Barker, John R.

doi:10.1109/led.2011.2177634

Cited by 72 publications

(30 citation statements)

References 17 publications

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“…16 The discrete dopants (donors) are each introduced as a positive electronic charge located in a 0.2 Â 0.2 Â 0.2 nm 3 volume. 10,11 Fig. 1 represents the structure and geometry of the simulated devices.…”

Section: Simulated Devices and Methodologymentioning

confidence: 99%

“…[7][8][9] Previous works carried out on quantum transport device simulation considering discrete dopants have been limited to small nanowire transistors. 10,11 These previous works showed that random discrete dopant fluctuations are a major source of statistical variability in 3D architectures. However, its impact is less detrimental than in planar architectures.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

Valin

Martı́nez

Barker

2015

Journal of Applied Physics

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Section: Simulated Devices and Methodologymentioning

confidence: 99%

mentioning

confidence: 99%

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

Valin

Martı́nez

Barker

2015

Journal of Applied Physics

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“…Although, the doping concentration in the source and drain regions is almost identical, σV TH in the tri-gate JLT is 7~9 times higher than that in the planar bulk MOSFET and SegFET. The random dopants along the channel in the JLT play a significant role in determining the threshold voltage, so that the higher channel doping concentration causes a large amount of V TH variation (in comparison with that in the planar bulk MOSFET and SegFET) [38,39].…”

Section: Junctionless Transistor (Jlt) [35 36]mentioning

confidence: 99%

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Nam¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (V TH ) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

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“…The theoretical foundations of JL FETs with double-gate [3], analysis of turned on characteristics of JL nanowire FET at different drain voltages and the potential under various operating conditions [4], discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations [5], the impact of random dopant fluctuation for several JL FinFET [6], et al can be searched. Furthermore, some modeling results such as theoretical model of the JL silicon-on-insulator (SOI) FET [7] and a charge-based model of DG MOSFETs [8] have been reported.…”

Section: Introductionmentioning

confidence: 99%

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

Wu¹,

Jin²,

Kwon³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The effect of band-to-band tunneling (BTBT) leads to an obvious increase of the leakage current of junctionless (JL) transistors in the OFF state. In this paper, we propose an effective method to decline the influence of BTBT with the example of ntype double gate (DG) JL metal-oxide-semiconductor field-effect transistors (MOSFETs). The leakage current is restrained by changing the geometrical shape and the physical dimension of the gate of the device. The optimal design of the JL MOSFET is indicated for reducing the effect of BTBT through simulation and analysis.

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Study of Discrete Doping-Induced Variability in Junctionless Nanowire MOSFETs Using Dissipative Quantum Transport Simulations

Cited by 72 publications

References 17 publications

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

Analysis of Random Variations and Variation-Robust Advanced Device Structures

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

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