Structured Bit-Interleaved LDPC Codes for MLC Flash Memory

Haymaker, Kathryn; Kelley, Christine A.

doi:10.1109/jsac.2014.140507

Cited by 18 publications

(6 citation statements)

References 16 publications

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“…A high speed implementation of this processing is described in [28]. The outer codes are constructed over the field GF(2 9 ), for which a non-pipelined GF multiplier is fast enough. Thus fewer registers are needed.…”

Section: Outer Decodermentioning

confidence: 99%

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Soft input decoder for high‐rate generalised concatenated codes

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Rohweder

Freudenberger

2018

IET Circuits, Devices & Systems

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Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a lowcomplexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

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Section: Outer Decodermentioning

confidence: 99%

“…coding schemes that can exploit soft information about the state of the memory cells. For instance, low-density parity-check (LDPC) can provide improved error correcting performance compared to BCH codes [6][7][8][9]. However, the implementation complexity of an LDPC decoder can be high when high data throughput should be achieved.…”

Section: Introductionmentioning

confidence: 99%

Soft input decoder for high‐rate generalised concatenated codes

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Rohweder

Freudenberger

2018

IET Circuits, Devices & Systems

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“…However, as Flash capacity continued to rise and MLCs gave way to TLCs, more efficient ECCs were needed, resulting in a transition to soft decoding schemes. Low-density parity-check (LDPC) ECCs [42][43][44][45] are gaining traction in modern SSDs, while concatenated codes for NAND Flash have been also proposed [46][47][48][49].…”

Section: Nand Flash Memory Reliabilitymentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…In order to exploit the reliability information soft input decoding algorithms are required. For instance, low‐density parity‐check (LDPC) codes can provide stronger error correcting performance [13–16]. However, LDPC codes can have high residual error rates (the error floor) and may not be suitable for applications that require very low decoder failure probabilities.…”

Section: Introductionmentioning

confidence: 99%