Structure and morphology of polycrystalline silicon-single crystal silicon interfaces

Abstract

Using high resolution transmission electron microscopy, morphological aspects of the polycrystalline silicon (polysilicon)-single crystal silicon interface have been correlated to the surface treatment used prior to polysilicon deposition, and to high-temperature annealing. Specimens which were chemically oxidized prior to the deposition exhibited a continuous layer of amorphous oxide ∼15 Å thick; high-temperature annealing results in the formation of small discontinuities in this oxide, and thus small regions of epitaxial realignment within the polysilicon layer. Specimens which were etched in HF prior to deposition were characterized by nearly oxide-free interfaces, and, following high-temperature annealing, exhibited regions of epitaxial realignment an order of magnitude larger than those found in the chemically oxidized samples.

Electrical and microstructural investigation of polysilicon emitter contacts for high-performance bipolar VLSI

“…The very high in situ doping level (1 X 10^' cm"' from SIMS), wet-etched emitter opening, and BHF cleaning before polysilicon deposition are favorable conditions for epitaxial realignment of the polysilicon. As shown in [8,10] and [7,9,11], high doping levels reduce the critical temperature for realignment and result in an increase in /^. Indeed, as shown in Figure 6, the base-current density of the emitter annealed at 900°C has reached a value close to what can be expected when the polysilicon is perfectly aligned to form an extended single-crystal emitter.…”

“…Since the largest current density in the device passes through the emitter contact, the specific contact resistivity must be kept as low as possible to prevent a degradation in tranKonductance. Although the exact electrical properties of the polysilicon/silicon interface are still under investigation, it is known that the interface structure changes significantly as a result of high-temperature anneaUng, and that these changes are enhanced at high doping levels [7][8][9][10][11]. Specifically, the "native" interface oxide layer "balls up" and the polysilicon tends to realign to the underlying substrate, thereby extending the single-crystal emitter up into the polysilicon layer.…”

Diffusion and segregation of arsenic and boron in polysilicon/silicon systems during rapid thermal annealing

“…According to Batra et al [9], the thickness of the oxide layer is estimated to be 1.4 and 0.8 nm for RCA cleaning and that one in HF, respectively. This latter treatment was observed by other authors [6,10,11] to lead to epitaxial realignment of the polycrystalline silicon during heat treatment.…”

Polysilicon/Silicon Interfaces: Effect of Processing Parameters on Physical and Electrical Properties

“…Atomically clean interfaces between the polysilicon and the substrate lead to the epitaxial realignment of the polysilicon [3]; interfaces that have a layer of thermal or chemical oxide, act as a diffusion barrier and prevent the implanted species from diffusing into the substrate [4] and hamper the formation of shallow junctions. Control of this interface has been attempted by cleaning the substrate with an aqueous etchant such as hydrofluoric acid [3] prior to polysilicon deposition or by growing a controlled amount of thermal oxide or deposited CVD nitride [4].…”