Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices

Mochizuki, Seibu; Colombeau, B.; Zhang, J.; Kung, Sheng-Chin; Stolfi, M.; Hong-Yu, Zhou; Breton, Mary; Watanabe, Kikuo; Li, J.; Jagannathan, H.; Mandrekar, T.; Chen, P.; Loubet, N.; Natarajan, S.; Haran, B.

doi:10.1109/vlsitechnology18217.2020.9265097

Cited by 6 publications

(2 citation statements)

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“…To improve their hole mobility, high-mobility SiGe- or GeSn-stacked channels have been introduced into p -type devices [ 41 ]. Mochizuki from IBM and coworkers [ 42 ] proposed a SiGe channel for p -type-stacked NS GAAFETs produced by channel trimming of 1–2 nm per side and conformal SiGe clamping layer epitaxial growth of 2–3 nm. Furthermore, a Si capping layer was applied as a passivation layer and D it was reduced by one order of magnitude.…”

Section: Transition From Finfet To Gaafetmentioning

confidence: 99%

New structure transistors for advanced technology node CMOS ICs

Zhang,

Luo

et al. 2024

National Science Review

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Over recent decades, advancements in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to 3D channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore’s law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFETs), 3D stack (3DS)-FETs and vertical-channel transistors, for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes, and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

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Section: Transition From Finfet To Gaafetmentioning

confidence: 99%

New structure transistors for advanced technology node CMOS ICs

Zhang,

Luo

et al. 2024

National Science Review

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“…The low-Ge-content SiGe channel will be implemented firstly on the FinFET owing to its advantages of higher hole mobility, better negative bias temperature instability (NBTI) reliability than silicon and more compatible with present silicon platform [ 4 , 5 ]. So far, a SiGe channel can be integrated in FinFET architectures in multiple ways, e.g., by shallow trench isolation (STI) last scheme [ 6 ] or by STI first strategy [ 7 ] or epitaxial cladding of Si Fins [ 8 ]. However, a high quality of low-Ge-content SiGe epitaxial grown on Si substrate is still a challenge task to solve the epitaxial thickness limit of SiGe film and the threading dislocations (TD) defects.…”

Section: Introductionmentioning

confidence: 99%

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

Zhao

Cheng

et al. 2021

Nanomaterials

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In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

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