Stress nature investigation on heteroepitaxial 3C–SiC film on (100) Si substrates

Abstract

To understand the impact that the growth rate has on the residual stress of chemical vapor deposition-grown 3C-SiC heteroepitaxial films on Si substrates, growth experiments were performed. The film thickness was held constant at ;2.5 lm independent of the growth rate so as to allow for direct film comparison as a function of the growth rate. Stress analysis performed by profilometer curvature measurement, livqo-Raman shift analysis and micro-machined freestanding structures, show an apparent disagreement about the stress nature. This incongruity between the experimental data can be explained assuming a strong stress field located in the substrate related to defects generated in the silicon during the growth process.

Optimization of growth parameters for growth of high quality heteroepitaxial 3C–SiC films at 1200°C

“…This reduction in temperature is beneficial for layers grown on large area substrates, which are not discussed here. The crystalline quality of the layers can compete with layers grown at much higher temperatures of up to 1380°C [8,19,23,24], which was confirmed by XRD-and Raman-measurements. A high C/Si-ratio, a low off-oriented substrate and a high layer thickness are required for the growth of high quality layers.…”

“…Most 3C-SiC/Si layers are grown at temperatures exceeding 1300°C and often the growth temperature is near the melting point of silicon. The reports at 1350°C by Chung and Kim [6] and by Portail et al [7] and at 1370°C by Anzalone et al [8] are just a few examples for high temperature grown 3C-SiC materials on Si. There are many attempts to grow at low temperatures e.g.…”

Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

“…at the carbonization step), where unspecified "defects" are generated in the silicon substrate. 18,19 Noting that the SiC/Si samples studied in this work were all grown at high temperatures, similar to that of Zielinski et al, and that all of the samples have shown electrical shorting with the silicon substrate, it seems logical to expect that this phenomenon must be related to a permanent change (plastic deformation) of the substrate (convex) curvature. This permanent curvature change must occur whenever the top portion of the silicon substrate is driven into compression (see schematic in Fig.3).…”

“…In addition, Anzalone et al, Camarda et al and Watts et al, have reported for SiC grown at 1300°-1400°C an intense compressive stress generated within the substrate capable of bowing the whole SiC/Si heterosystem downwards. [18][19][20] These authors also proposed the stress originated from the early stage of growth (i.e. at the carbonization step), where unspecified "defects" are generated in the silicon substrate.…”

Effect of C/Si Moore Ratio on the Morphology and Crystallinity of 3C-SiC/Si(100) by the Modified Two-Step Carbonization Process

“…et al [8], Chung G.S. et al [9], and Anzalone R. et al [10] have grown 3C-SiC films on Si substrates at 1200 °C, 1350 °C and 1370 °C respectively. The crystalline quality and surface morphology of 3C-SiC films were the most important factors that affected manufacture of 3C-SiC/Si devices [11].…”