Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors

“…Also, we skip offset-spacer formation to avoid the creation of underlapped devices. We adopted stress memorization technique and dual stress liners [5]. As our reference, we use PDSOI wafers with 70-nm-thick SOI, 145-nm-thick BOX, appropriate well and halo doping, and gate-to-SDE overlap similar to the ETSOI devices [10].…”

Study of strained-silicon channel metal–oxide–semiconductor field effect transistors by large angle convergent-beam electron diffraction

“…To epitaxially grow strained-silicon on a relaxed SiGe layer can introduce biaxial tensile strain to the channel due to the lattice mismatch between Si and SiGe [2][3][4][5][6], but the progress has been hindered by the lack of low-cost, highquality strained-Si substrate and the challenges in materials and process integration though transistor performance enhancement has been reported. In addition, the strain effects can be induced during the fabrication process, such as contact etch stop liner [8,9], stress memorization technique [10,11], embedded SiGe alloy in the source/drain (S/D) [12]. Recently, Ge pre-amorphization implantation (Ge PAI) in the S/D region was used to realize substantially enhanced compressive strain and carrier mobility in the channel of p-type metal-oxide-semiconductor field effect transistors (pMOSFETs) [13].…”

“…The key challenge for existing strain engineering methods [2][3][4][5][6][7][8][9][10][11][12] is how to obtain large enough strains without inducing defects through low-cost integration of the actual semiconductor technology. The main techniques for introducing strain into the channel are substrate based [2][3][4][5][6] and process induced [7][8][9][10][11][12]. To epitaxially grow strained-silicon on a relaxed SiGe layer can introduce biaxial tensile strain to the channel due to the lattice mismatch between Si and SiGe [2][3][4][5][6], but the progress has been hindered by the lack of low-cost, highquality strained-Si substrate and the challenges in materials and process integration though transistor performance enhancement has been reported.…”

Femtosecond forsterite Kerr-lens mode-locked laser pumped synchronously by an Nd3+:YAG laser

“…Recently, to obtain further current-drive enhancement, multiple-stressor technology (MST) has been introduced, in which a combination of two or more strained silicon technologies is applied to achieve a much higher channel strain. [2][3][4][5][6] Indeed, excellent performance has been demonstrated with MST, however, issues regarding such a high-stress device have not been well-discussed. In this paper, focusing on MST, we explore its impact on scaled devices for the 45 nm technology node, and the resulting issues that have become pronounced under extremely high channel strains are comprehensively investigated.…”