2005
DOI: 10.1149/1.1905970
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Stress Corrosion Cracking of Cu Interconnects during CMP with a Cu/Porous Low-k Structure

Abstract: Porous low-k materials are required in the construction of 45 nm node large-scale integrated devices. However, the extremely low Young's modulus values of these materials results in a high number of previously unreported defects. A porous low-k film stacked with a dense low-k film showed pronounced cracking in its Cu wiring, which was concentrated in isolated lines 0.18 m in width and was accelerated with longer chemical-mechanical polishing ͑CMP͒ times. Denser lines showed less cracking and the single structu… Show more

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Cited by 21 publications
(38 citation statements)
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References 9 publications
(12 reference statements)
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“…Figure 2 shows that the PDS concentration increases from 0 to ϳ30 ppm as the bath idle-time increases from 0 to 20 days. 16 The result is consistent with the data of Fig. Long narrow strip defects such as scraping on the Cu surface are defined as scratch defects, and hollow hole defects such as removing a lump of Cu are defined as void defects.…”
Section: Resultssupporting
confidence: 89%
See 1 more Smart Citation
“…Figure 2 shows that the PDS concentration increases from 0 to ϳ30 ppm as the bath idle-time increases from 0 to 20 days. 16 The result is consistent with the data of Fig. Long narrow strip defects such as scraping on the Cu surface are defined as scratch defects, and hollow hole defects such as removing a lump of Cu are defined as void defects.…”
Section: Resultssupporting
confidence: 89%
“…Moffat et al proposed the kinetics of Cu electroplating in a cupric-sulfate electrolyte containing SPS-polyethylene glycol ͑PEG͒-Cl. [10][11][12][13][14][15][16][17][18] Conventional CMP slurries usually contain strong oxidizers and hard abrasives, easily leading to the formation of various defects on Cu metals. 8,9 Chemical mechanical polishing ͑CMP͒ is the most promising way to remove overburdened metals to realize planarization in the damascene metallization process.…”
Section: Introductionmentioning
confidence: 99%
“…These undergo multiple failure mechanisms such as delamination [4], channel cracking [5,6] and surface cracking which can be coupled with time-dependent damage from load cycling [7] and environmental degradation [8]. While multiple techniques and analyses exist for studying delamination or channel cracking of deposited thin films, direct measurements of fracture toughness values are relatively rare.…”
Section: Introductionmentioning
confidence: 99%
“…Introducing pores in a dielectric poses several challenges for successful integration into microelectronic circuits [17,18]. The mechanical strength of the dielectric is reduced by porosity, potentially leading to failure during chemical mechanical planarization (CMP) [19,20,21,22] or during wire bonding to the fi nished chip [23]. In addition, moisture, wet chemicals and gaseous species (such as precursors used during CVD) can penetrate into porous low-k materials, giving rise to an increase in both the dielectric constant and the leakage current [24].…”
Section: Introductionmentioning
confidence: 99%