Porous low-k materials are required in the construction of 45 nm node large-scale integrated devices. However, the extremely low Young's modulus values of these materials results in a high number of previously unreported defects. A porous low-k film stacked with a dense low-k film showed pronounced cracking in its Cu wiring, which was concentrated in isolated lines 0.18 m in width and was accelerated with longer chemical-mechanical polishing ͑CMP͒ times. Denser lines showed less cracking and the single structure of a dense low-k film showed no cracking. We hypothesized that this cracking might be categorized as stress corrosion cracking ͑SCC͒. Accordingly, we investigated the relation between stress and corrosion in certain kinds of slurry. We have also researched the effects on corrosion of temperature and various metals. In all of the slurry that we tested, tensile stress increased corrosion current in Cu samples. Furthermore, both finite element method analysis of stress during CMP and measurements of friction on the Cu/low-k surface by scanning probe microscopy indicated concentration of stress on low-k materials, especially at the edges of isolated wiring. Thus, we concluded that stress enhances corrosion during CMP and that there was a high possibility of SCC.

SUMMARYIn recent years, Cu/low-k damascene (buried interconnects) processing, which uses Cu interconnects with low-dielectric-constant (low-k) films, has emerged as a way to satisfy the requirements for making devices ultrasmall, high-speed, and usable in ultralarge-scale integration (ultra-LSI). However, the use of Cu in combination with new materials to make the low-k films has led to difficulties in developing a process for cleaning after post-chemical-mechanical planarization (CMP). One of these problems is the presence of hydrophobic residuals on the low-k films, for whose removal many slurries (polishing agents) and cleaning fluids have been developed. In our work, we have combined these slurries and cleaning fluids, and investigated the effectiveness of the combinations in cleaning low-k films, allowing us to develop an optimum process. We determined the defect counts for TEOS, Cu, and two kinds of low-k films, and measured the level of contamination of the low-k film contaminant by spots of Cu, from which we identified cleaning fluid that performed best. We also confirmed that the performance of the cleaning fluids was different depending on the choice of slurry. We then used our optimum process to formulate a fabrication scheme for devices with the Cu/low-k structure, fabricated a set of devices, and investigated their electrical characteristics. Because of the significant reduction we observed in leakage currents between circuit lines to below 10 -9 to 10 -10 A/m, we argue that our process can be used to fabricate ultra-LSI device ensembles under real conditions.

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