Strategies for single patterning of contacts for 32nm and 28nm technology

Morgenfeld, Bradley; Stobert, Ian; Haffner, Henning; An, Juj; Kanai, Hideki; Ostermayr, Martin; Chen, Norman; Aminpur, M.; Brodsky, Colin J.; Thomas, A.

doi:10.1109/asmc.2011.5898207

Cited by 5 publications

(4 citation statements)

References 4 publications

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“…In addition, the minimum distance in-between the two contacts needs to be maintained. More discussion and examples for non-square contacts can be found in [36].…”

Section: Non-square Contactsmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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“…In addition, the minimum distance in-between the two contacts needs to be maintained. More discussion and examples for non-square contacts can be found in [36].…”

Section: Non-square Contactsmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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“…1,2 Innovations that may enable future technologies include EUV lithography 3 and directed self-assembly. With each new technology, new photolithography innovations are required.…”

Section: Introductionmentioning

confidence: 99%

Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology

Ryan

Patterson

Lei

et al. 2015

J. Micro/Nanolith. MEMS MOEMS

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Early in-line detection of systematic patterning problems in technology development can dramatically improve a technology's chance for success. By uncovering layout geometries that are difficult to implement, prompt action may be taken so that solutions are in place well before product chips that contain these and similar patterns enter the manufacturing line. If a solution is not in place, this could spell disaster for the product and perhaps even the technology. Ideally, product chips will work on the first lot, which is referred to as "first time right." To help ensure this, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) was developed. We review this methodology, including the latest enhancements. Pattern simulation tools and other sources are used to provide die locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses any hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Application of this methodology to a fin-shaped field effect transistor technology is described using examples from the fin and back end of line modules. These examples illustrate the full range of actions used to resolve patterning issues. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/02/2015 Terms of Use: http://spiedl.org/terms Ryan et al.: Application of E-beam hot spot inspection for early detection of systematic patterning problems. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/02/2015 Terms of Use: http://spiedl.org/terms

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“…Increasingly complex lithography techniques, including double patterning, source-mask optimization and more complicated OPC schemes, are being used to address this [1], [2]. The lithography process is extensively simulated and test patterns are even printed on wafers to check the design data preparation algorithms used to generate the masks.…”

Section: Introductionmentioning

confidence: 99%

E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

Patterson

Ryan

Monkowski

et al. 2014

IEEE Trans. Semicond. Manufact.

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Early detection of systematic patterning problems can provide a major boost for a technology team. Often in the past, these type defects might only be detected after functional test and subsequent failure analysis. At this point, three to six months of process development time have been lost and three to six months of defective hardware have been wasted. In this paper, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) is introduced. Pattern simulation tools and other sources are used to recommend X, Y locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses the hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Often, additional data is necessary to determine the full yield impact. This methodology provided tremendous value for IBM's 22 nm SOI technology.Several examples illustrating this point are presented. Line monitoring after the process windows have been established is also discussed.Index Terms-Hot spot inspection, E-beam inspection, ORC, OPC, pattern fidelity.

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Strategies for single patterning of contacts for 32nm and 28nm technology

Cited by 5 publications

References 4 publications

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology

E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

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