E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

Patterson, Oliver D.; Ryan, Deborah A.; Monkowski, M.D.; Nguyen-Ngoc, D.; Morgenfeld, Bradley; Lee, Chung-Han; Liu, Chieh-Hung; Chen, Shih-tsung; Lei, Shuen-Cheng Chris

doi:10.1109/tsm.2014.2358214

Cited by 6 publications

(3 citation statements)

References 6 publications

(5 reference statements)

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“…After images acquisition, image quality are verified with precision test, distortion correction and focus index. Then high performance computers (HPCs) system -SuperNova (SN) with D2DB (die-to-database) imaging-to-GDS function [8] is used to extract CD metrology data and defect inspection [9] data with ellipse fitting algorithm and automated defect classification (ADC) training, respectively. The generated CD and Defects dataset as well as exposure report are the inputs for FEM based process window analysis.…”

Section: Metrology and Pwm Data Analysismentioning

confidence: 99%

Evaluation of high NA thin resist metrology and stochastic performance

Wu,

Freeman,

Elmalk

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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The next milestone in the resolution of high-volume manufacturing will be achieved by High-NA EUV Lithography (HiNA EUVL) systems. In addition to the development of high-NA EUV scanners, the implementation of next generation resist materials remains a critical challenge. Thinner resists are required to accommodate DoF decrease on higher NA physics, which may lead to e-beam metrology and e-beam inspection sensitivity loss due to less electron signal and more severe stochastic failures and variabilities. Due to worse resist imaging contrast and larger pattern roughness in HiNA EUVL, accurate and high resolution CD and defect metrology as well as precise process window (PW) evaluation which considers stochastic failure rate (FR) are needed for resist screening to support the gradual reduction of resist thickness.In this paper we present a thin resist evaluation flow based on next generation e-beam metrology tool (eP6), including metrology setup and qualification and stochastic-aware process window (SAPW) analysis. We will show ADI (after development imaging) evaluation results for a contact hole array with pitch of 32nm for three CAR resist deposited thicknesses from 60nm to 30nm (note: ~40% resist thickness loss post-development). First, we will illustrate some of the metrology responses associated with thin resist and highlight the benefits of improved precision (0.7x), resolution (1.5nm) and sensitivity of next generation metrology tool. For each resist thickness, we will show CD, LCDU and defect measurements across a focus-exposure matrix. LCDU decomposition will be used to quantify SEM, mask, and stochastic contributions to the total measured LCDU. Finally, we will exhibit the SAPW result (Dose-to-Size, Depth of Focus, Exposure Latitude … etc) for the range of resist thicknesses, which can be used to optimize process centering and qualify thin resist performance for HiNA with high correlation coefficient (> 0.9) between measured FR and modeled FR.

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Section: Metrology and Pwm Data Analysismentioning

confidence: 99%

Evaluation of high NA thin resist metrology and stochastic performance

Wu,

Freeman,

Elmalk

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

View full text Add to dashboard Cite

show abstract

“…For instance, to assist understanding of complex process interactions, virtual-fabrication process emulation was employed [25]. We also made use of innovative detection capability such as high-resolution electron-beam hotspot inspection on complex two-dimensional constructs at the 1X metal levels [26].…”

Section: Meeting Product Schedule With Rapid Yield Learningmentioning

confidence: 99%

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

et al. 2015

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IBM's high-performance 22-nm silicon-on-insulator (SOI) technology is the enabling physical foundation of IBM POWER8i processors. This paper describes, for the first time in detail, some of the unique aspects of the silicon processing, the features that enabled the industry-leading chip-level performance, and some aspects of the collaborative approach between technology and design teams that enabled both first-time-right silicon and rapid yield improvement. Most critical to the processor functional capability and power-performance achievements are the high-density on-chip memory in the form of embedded DRAM and the high-performance FET device designs based on a low-parasitic-capacitance gate-first FET architecture. Extensive on-chip analog functions are enabled by an additional comprehensive set of devices available in the technology. Fifteen levels of metal with five metal levels at an 80-nm pitch provide the interconnect and power distribution. We describe the pattern resolution enhancement strategy as well as motivation and structural aspects of the innovative features, from the low-resistance N+ epitaxy substrate under the SOI to a dual-embedded source-drain architecture and a highly scaled gate dielectric.

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“…5 This methodology requires a physical inspection condition, where the physical pattern of the material is compared 6 as opposed to a voltage contrast inspection condition, where voltages are induced on the wafer surface and compared. 5 This methodology requires a physical inspection condition, where the physical pattern of the material is compared 6 as opposed to a voltage contrast inspection condition, where voltages are induced on the wafer surface and compared.…”

Section: Introductionmentioning

confidence: 99%

Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology

Ryan

Patterson

Lei

et al. 2015

J. Micro/Nanolith. MEMS MOEMS

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Early in-line detection of systematic patterning problems in technology development can dramatically improve a technology's chance for success. By uncovering layout geometries that are difficult to implement, prompt action may be taken so that solutions are in place well before product chips that contain these and similar patterns enter the manufacturing line. If a solution is not in place, this could spell disaster for the product and perhaps even the technology. Ideally, product chips will work on the first lot, which is referred to as "first time right." To help ensure this, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) was developed. We review this methodology, including the latest enhancements. Pattern simulation tools and other sources are used to provide die locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses any hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Application of this methodology to a fin-shaped field effect transistor technology is described using examples from the fin and back end of line modules. These examples illustrate the full range of actions used to resolve patterning issues. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/02/2015 Terms of Use: http://spiedl.org/terms Ryan et al.: Application of E-beam hot spot inspection for early detection of systematic patterning problems. . . Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 06/02/2015 Terms of Use: http://spiedl.org/terms

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E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

Cited by 6 publications

References 6 publications

Evaluation of high NA thin resist metrology and stochastic performance

Evaluation of high NA thin resist metrology and stochastic performance

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM

Application of E-beam hot spot inspection for early detection of systematic patterning problems to a FinFET technology

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