Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO&lt;inf&gt;2&lt;/inf&gt; gate stack

Barral, V.; Poiroux, T.; Andrieu, F.; Buj-Dufournet, C.; Faynot, O.; Ernst, T.; Brévard, L.; Fenouillet-Béranger, C.; Lafond, D.; Hartmann, Jean‐Michel; Vidal, V.; Allain, F.; Daval, N.; Cayrefourcq, I.; Tosti, L.; Munteanu, Daniéla; Autran, Jean‐Luc; Deleonibus, S.

doi:10.1109/iedm.2007.4418863

Cited by 43 publications

(40 citation statements)

References 7 publications

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“…The electric field can tune single donor states and quantum dot-like states in our device [12][13][14] . For more details on the device structure and fabrication refer to Barral et al 15 .…”

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confidence: 99%

Radio-frequency dispersive detection of donor atoms in a field-effect transistor

2014

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Radio-frequency dispersive read-out can provide a useful probe to nano-scale structures such as nano-wire devices, especially when the implementation of charge sensing is not straightforward. Here we demonstrate dispersive 'gate-only' read-out of phosphor donors in a silicon nano-scale transistor. The technique enables access to states that are only tunnel-coupled to one contact, which is not easily achievable by other methods. This allows us to locate individual randomly placed donors in the device channel. Furthermore, the setup is naturally compatible with high bandwidth access to the probed donor states and may aid the implementation of a qubit based on coupled donors.

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confidence: 99%

Radio-frequency dispersive detection of donor atoms in a field-effect transistor

2014

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“…The conservation and enhancement of strain can be observed in very thin layers with small gate lengths. The saturation current can be improved by 40% at the L g =18 nm level by combining strain and ballistic transport [34,35]. I off levels in the pA/µm range have been obtained in these devices with Si thicknesses as low as 2.5 nm [35] (Figures 9 and 10).…”

Section: Quasi-ballistic Transport In Strained Fdsoi Devicesmentioning

confidence: 88%

“…The saturation current can be improved by 40% at the L g =18 nm level by combining strain and ballistic transport [34,35]. I off levels in the pA/µm range have been obtained in these devices with Si thicknesses as low as 2.5 nm [35] (Figures 9 and 10). In this devices architecture, ballistic rates BR of 50% were obtained at room temperature and did not exceed 60% at 50 K (n and p MOS with T si =6 nm N INV =6 × 10 12 cm −2 ) [8,9].…”

Section: Quasi-ballistic Transport In Strained Fdsoi Devicesmentioning

confidence: 88%

“…However, in small devices, high electric fields affect the transport mechanisms. Therefore, transport must be considered quasi ballistic, involving: 1) repopulation of heavy effective mass sub-bands guided by degenerate statistics under high electric fields; and 2) backscattering of carriers by coulombic sites (interfaces and dopants) [6][7][8][9]. In the saturation regime, the drain current will be reduced by the ballisticity rate depending primarily on the backscattering of the injected carriers.…”

Section: Non Stationary Transportmentioning

confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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“…A significant part of these electrodes are applied in the DRAM memory cell [2,3]. But also in gate stack development for advanced CMOS beyond 45 nm technology node TiN is widely used as mid-gap metal gate electrode [4]. The material is applied as control gate electrode in NAND Flash [5], as well as heater electrode and control gate electrodes in phase change memory [6].…”

Section: Introductionmentioning

confidence: 99%

Novel Batch Titanium Nitride CVD Process for Advanced Metal Electrodes

et al. 2008

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This article describes a novel CVD process for Titanium Nitride (TiN) films developed in a 300 mm vertical furnace. We have solved Chlorine incorporation at low temperature inside the TiN layer while at the same time the batch process yields a 3 times higher throughput per dual reactor system compared to a single wafer system with 3 chambers. We show process results for load sizes ranging from 5 to as much as 100 wafers that prove filler wafers are only required to a minimum. Applications with the developed TiN process are in Metal-Insulator-Metal memory devices such as Stack DRAM, and embedded DRAM.

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Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO<inf>2</inf> gate stack

Cited by 43 publications

References 7 publications

Radio-frequency dispersive detection of donor atoms in a field-effect transistor

Radio-frequency dispersive detection of donor atoms in a field-effect transistor

Ultra-thin films and multigate devices architectures for future CMOS scaling

Novel Batch Titanium Nitride CVD Process for Advanced Metal Electrodes

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