Strain mapping for advanced CMOS technologies

Abstract

The ability to measure strain quantitatively has become an important tool for characterizing strain-engineered CMOS devices. We report on nanometer scale strain measurements performed on off-the-shelf 32-nm node device structures. We show that the two-dimensional deformation tensor in NMOS channels can be mapped using high resolution transmission electron microscopy. We also demonstrate the application of our recently developed dark-field inline holography technique on an array of PMOS transistors, showing that this technique is capable of combining a large field of view of 1 micrometer with a spatial resolution better than 1 nm, and very high precision (around 10 −4 ). Also, the experimental requirements for implementing this technique are easily met on most modern TEMs, without any modification to the hardware or alignment of the microscope.

Micro-to-nano Scale Strain Characterization of 2024 Aluminum-alloys with Incoherent/Coherent Precipitates

“…In this study, we characterized a region with three different precipitates oriented in the plan normal to the sample. We first acquired high-resolution scanning TEM images of these three precipitates and used geometrical phase analysis (GPA) algorithm to obtain strain mapping close to one nanometer scale [1]. Due to the configuration of the TEM used for this experiment (absence of probe corrector), the field of view with this technique is limited to 20 nm x 20 nm area.…”