The control and rational design of redox-based memristive devices, which are highly attractive candidates for next-generation nonvolatile memory and logic applications, is complicated by competing and poorly understood switching mechanisms, which can result in two coexisting resistance hystereses that have opposite voltage polarity. These competing processes can be defined as regular and anomalous resistive switching. Despite significant characterization efforts, the complex nanoscale redox processes that drive anomalous resistive switching and their implications for current transport remain poorly understood. Here, lateral and vertical mapping of O vacancy concentrations is used during the operation of such devices in situ in an aberration corrected transmission electron microscope to explain the anomalous switching mechanism. It is found that an increase (decrease) in the overall O vacancy concentration within the device after positive (negative) biasing of the Schottky-type electrode is associated with the electrocatalytic release and reincorporation of oxygen at the electrode/oxide interface and is responsible for the resistance change. This fundamental insight presents a novel perspective on resistive switching processes and opens up new technological opportunities for the implementation of memristive devices, as anomalous switching can now be suppressed selectively or used deliberately to achieve the desirable so-called deep Reset.

Silicon photonics continues to progress tremendously, both in near-infrared datacom/telecoms and in mid-IR optical sensing, despite the fact a monolithically integrated group IV semiconductor laser is still missing. GeSn alloys are one of the most promising candidate materials to realize such devices, as robust lasing under optical pumping was demonstrated by several groups up to mild cryogenic temperatures. Ideally, the integrated lasers should be tunable by design over a wide spectral range, offering a versatility that is required for optical sensing devices. We present here an innovative approach, taking advantage of local strain management in the semiconductor laser’s active zone. Arrays of differently strained Fabry-Pérot GeSn microlasers were fabricated side-by-side on the very same chip after blanket epitaxy on a Ge-buffered silicon-on-insulator substrate. Thanks to the local strain design, laser emission over a very large wavelength range under optical pumping, with laser lines peaking from 3.1 up to 4.6 μm at 25 K and with thresholds lower than 10 kW·cm–2. Laser operation persists up to 273 K, that is, very close to room temperature. This strategy, implemented on group IV semiconductors, opens up a new route to control the emission properties of microlasers integrated on a chip over significant photon energy windows representing a significant step forward in the integration and miniaturization of light sources emitting at a process-defined wavelength.

The last few years have seen a great deal of progress in the development of transmission electron microscopy based techniques for strain mapping. New techniques have appeared such as dark field electron holography and nanobeam diffraction and better known ones such as geometrical phase analysis have been improved by using aberration corrected ultra-stable modern electron microscopes. In this paper we apply dark field electron holography, the geometrical phase analysis of high angle annular dark field scanning transmission electron microscopy images, nanobeam diffraction and precession diffraction, all performed at the state-of-the-art to five different types of semiconductor samples. These include a simple calibration structure comprising 10-nm-thick SiGe layers to benchmark the techniques. A SiGe recessed source and drain device has been examined in order to test their capabilities on 2D structures. Devices that have been strained using a nitride stressor have been examined to test the sensitivity of the different techniques when applied to systems containing low values of deformation. To test the techniques on modern semiconductors, an electrically tested device grown on a SOI wafer has been examined. Finally a GaN/AlN superlattice was tested in order to assess the different methods of measuring deformation on specimens that do not have a perfect crystalline structure. The different deformation mapping techniques have been compared to one another and the strengths and weaknesses of each are discussed.

Van der Waals layered GeTe/Sb Te superlattices (SLs) have demonstrated outstanding performances for use in resistive memories in so-called interfacial phase-change memory (iPCM) devices. GeTe/Sb Te SLs are made by periodically stacking ultrathin GeTe and Sb Te crystalline layers. The mechanism of the resistance change in iPCM devices is still highly debated. Recent experimental studies on SLs grown by molecular beam epitaxy or pulsed laser deposition indicate that the local structure does not correspond to any of the previously proposed structural models. Here, a new insight is given into the complex structure of prototypical GeTe/Sb Te SLs deposited by magnetron sputtering, which is the used industrial technique for SL growth in iPCM devices. X-ray diffraction analysis shows that the structural quality of the SL depends critically on its stoichiometry. Moreover, high-angle annular dark-field-scanning transmission electron microscopy analysis of the local atomic order in a perfectly stoichiometric SL reveals the absence of GeTe layers, and that Ge atoms intermix with Sb atoms in, for instance, Ge Sb Te blocks. This result shows that an alternative structural model is required to explain the origin of the electrical contrast and the nature of the resistive switching mechanism observed in iPCM devices.

We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe sourcedrain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

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We investigate the growth of the recently demonstrated composite material composed of vertically aligned carbon nanotubes capped by few graphene layers. We show that the carbon nanotubes grow epitaxially under the few graphene layers. By using a catalyst and gaseous carbon precursor different from those used originally we establish that such unconventional growth mode is not specific to a precise choice of catalyst-precursor couple. Furthermore, the composite can be grown using catalyst and temperatures compatible with CMOS processing (T < 450 • C).