Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

Abstract

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing trend is given.

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

“…Mobility enhancement is in turn a very attractive option because it improves device performance beyond the benefits provided by scaling 1 . Mobility enhancement can be achieved by altering the properties of silicon through strain-induced manipulation of the band structure, which modifies the effective masses and phonon scattering within the channel 4 . For these reasons, silicon NWs with strained channels are promising candidates for the next generation of MOSFETs 5 .…”

“…Because the dimensions of current scaled transistors are becoming smaller than the required thickness of such an overlayer, it is difficult to implement this approach into smaller nodes while providing uniaxial tensile stress higher than the presently obtained ~2 GPa (corresponding to ~1.2% strain) 4,6 . Indeed, the integration of strain levels higher than those currently available into silicon NWs is recognized as a major milestone for the front end silicon technology at smaller nodes 7 .…”

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

“…To extract the low-field electron mobility, a cylindrical model, similar to [16], was used to expect the C ox value for the GAA deeply scaled nanowires. In this work, the extracted low-field electron mobility at V DS = 100 mV is 332 cm 2 /V s, 32% higher than bulk Si electron mobility at the same level of doping (1 Â 10 18 cm À3 ) [17], which is an evidence of including uniaxial tensile stress in the channel, and possibly a higher level can be achieved in this level of stress [7] in the case of an optimum dielectric-channel interface quality especially for the deeply scaled channels [18]. Fig.…”

“…5 and 6 represent the transfer, transconductance and output characteristic of a GAA AMOSFET including an array of 10 deeply scaled Si nanowires in h1 1 0i orientation, depicted SEM and TEM micro/nanographs in Fig. 3, at 298 K. The h1 1 0i orientated Si nanowire devices were chosen simply to investigate the highest uniaxial tensile stress-induced performance [7].…”

“…According to [7], the electron mobility enhancement is saturating in the Si-based MOSFETs by including >2.0 GPa uniaxial tensile stress in the channel and therefore, the highest nominal electron mobility enhancement is already expected in such bended Si nanowires. A more in-depth stress study in [8] reveals that the uniaxial tensile stress/strain level for similar 2.0 lm long GAA Si nanowires can be up to 5.6 GPa/3.3% considering both in-plane and out-ofplane buckling using both top and tilted-view SEM micrographs.…”