Stopper-less hybrid low-k/Cu DD structure fabrication combined with low-k CMP

Usami, T.; Nanbu, H.; Sugai, Kazumi; Tagami, M.; Miyamoto, H.

doi:10.1109/iitc.2002.1014948

Cited by 2 publications

(2 citation statements)

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“…This success of the simpler and hence, manufacturable integration with less materials and interfaces is attributed to the capability of modern dry etching tools which have controllability and uniformity across the wafer enough to support the pattern definition in the monolithic damascene scheme. Another example to show the strong dependency on the tool/material/process capability and readiness is the across-the-wafer non-uniformity of modern CMP tools which so far seem unable to support the Hard Mask Retention scheme for the use of ULK at the trench level for the 65 nm node BEOL technologies in the manufacturing phase, although a bunch of damascene schemes have been reported [18][19][20][21][22][23][24].. Thus, discussions on possibility of implementation of ULK in the 45 nm node BEOL must be made on certain assumptions about the tool capability/readiness and limitation for manufacturing [25][26][27].…”

Section: Technical Challenges To the 45 Nm Beol Processmentioning

confidence: 97%

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Nogami

Lane²,

Fukasawa

et al. 2005

SPIE Proceedings

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This paper discusses low-k/copper integration schemes which has been in production in the 90 nm node, have been developed in the 65 nm node, and should be taken in the 45 nm node. While our baseline 65 nm BEOL process has been developed by extension and simple shrinkage of our PECVD SiCOH integration which has been in production in the 90 nm node with our SiCOH film having k=3.0, the 65 nm SiCOH integration has two other options to go to extend to lower capacitance. One is to add porosity to become ultra low-k (ULK). The other is to stay with low-k SiCOH, which is modified to have a "lower-k". The effective k-value attained with the lower-k (k=2.8) SiCOH processed in the "Direct CMP" scheme is very close to that with an ULK (k=2.5) SiCOH film built with the "Hard Mask Retention" scheme. This paper first describes consideration of these two damascene schemes, whose comparison leads to the conclusion that the lower-k SiCOH integration can have more advantages in terms of process simplicity and extendibility of our 90 nm scheme under certain assumptions. Then describing the k=2.8 SiCOH film development and its successful integration, damascene schemes for 45nm nodes are discussed based on our learning from development of the lower-k 65nm scheme. Capability of modern dry etchers to define the finer patterns, nonuniformity of CMP, and susceptibility to plasma and mechanical strength and adhesion of ULK are discussed as factors to hamper the applicability of ULK.

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Section: Technical Challenges To the 45 Nm Beol Processmentioning

confidence: 97%

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Nogami

Lane²,

Fukasawa

et al. 2005

SPIE Proceedings

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“…The interconnect structure called a hybrid structure which uses different interlayer dielectrics for Cu trench and Cu vias is investigated. 3,4 The middle stopping layer can be eliminated in the hybrid structure because a high selectivity of dry etching rates can be obtained between the dielectrics for the trench and the via. CoWP having the resistance of Cu diffusion was formed with the electroless deposition in the upper part of the trench in order to eliminate the passivation layer arranged on the trench wiring.…”

mentioning

confidence: 99%

Recovery Processes of CMP-Induced Damages for Copper/Porous Silica Damascene Interconnects

Ishikawa

Shishida

Yamanishi

et al. 2007

J. Electrochem. Soc.

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This paper describes the effects of recovery processes for the degradation caused by chemical mechanical polishing ͑CMP͒ in the integration of Cu/porous silica low-k material interconnects ͑Cu/po-SiO͒, in which SiOC is used as CMP-Cap film ͑Cap-SiOC͒ for po-SiO film. The leakage current and capacitance between Cu damascene interconnects increased when Cap-SiOC was removed by CMP and the po-SiO was exposed, because the surfactant in CMP chemicals penetrated the po-SiO and the hydrophobicity of the po-SiO decreased, resulting in the increase of water absorption in the po-SiO. As a result of the recovery process after CMP, the leakage current has decreased by three orders of magnitude by applying an isopropyl alcohol rinse and 1,3,5,7-tetramethylcyclo-tetrasiloxane ͑TMCTS͒ gas treatment, and the capacitance has decreased by 15% by applying the TMCTS gas treatment.

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Stopper-less hybrid low-k/Cu DD structure fabrication combined with low-k CMP

Cited by 2 publications

References 1 publication

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Low-k/copper integration scheme suitable for ULSI manufacturing from 90nm to 45nm nodes

Recovery Processes of CMP-Induced Damages for Copper/Porous Silica Damascene Interconnects

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