2007
DOI: 10.1149/1.2711078
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Recovery Processes of CMP-Induced Damages for Copper/Porous Silica Damascene Interconnects

Abstract: This paper describes the effects of recovery processes for the degradation caused by chemical mechanical polishing ͑CMP͒ in the integration of Cu/porous silica low-k material interconnects ͑Cu/po-SiO͒, in which SiOC is used as CMP-Cap film ͑Cap-SiOC͒ for po-SiO film. The leakage current and capacitance between Cu damascene interconnects increased when Cap-SiOC was removed by CMP and the po-SiO was exposed, because the surfactant in CMP chemicals penetrated the po-SiO and the hydrophobicity of the po-SiO decrea… Show more

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Cited by 4 publications
(3 citation statements)
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“…Major problems are delamination caused by chemical mechanical planarization and drastic change in the dielectric due to pore-induced damage occurring in the wet cleaning and ashing processes. Since porous SiOCH occupies a lot of space in a film, it is fragile and readily absorbs any solutions or gases [1][2][3][4][5]. Moreover, Cu atoms easily diffuse into the SiOCH through pores.…”
Section: Introductionmentioning
confidence: 99%
“…Major problems are delamination caused by chemical mechanical planarization and drastic change in the dielectric due to pore-induced damage occurring in the wet cleaning and ashing processes. Since porous SiOCH occupies a lot of space in a film, it is fragile and readily absorbs any solutions or gases [1][2][3][4][5]. Moreover, Cu atoms easily diffuse into the SiOCH through pores.…”
Section: Introductionmentioning
confidence: 99%
“…In this work, we investigate the effect of the CMP process on low-k/Cu monolithic structures fabricated using local CMP technology. [1][2][3][4] Figure 2 illustrates features of the local CMP apparatus, where a rotating polishing head with a CMP pad smaller than the 300 mm wafer scans the wafers, which are oriented face-up on a rotating chuck. The compact CMP head rotates at high speeds of up to 400 rpm and applies a precise polishing pressure of as low as 0.05 psi.…”
Section: Introductionmentioning
confidence: 99%
“…It also gives rise to dielectric degradation and high tooling cost. 2,3 When new materials for conductors, barrier layers, and dielectrics are introduced for future nanodevices, the slurry and stop layer for the CMP process must be investigated to meet surface planarization. Yamada et al 4 studied the influence of CMP and post-CMP cleaning process on the electrical characteristic of Cu/silicon oxycarbide.…”
mentioning
confidence: 99%