Stochastic computation

Shanbhag, Naresh R.; Abdallah, Rami A.; Kumar, Rakesh; Jones, Douglas L.

doi:10.1145/1837274.1837491

Cited by 122 publications

(70 citation statements)

References 20 publications

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“…Error probability can be traded off with design metrics by adjusting verification thresholds, or selective guardbanding, or selective redundancy, etc. Recent work ("stochastic computing" [79]) advocates that hardware should be allowed to produce errors even during nominal operation if such [20] design is to transform a slack distribution characterized by a critical wall into one with a more gradual failure characteristic. This allows performance/power tradeoffs over a range of error rates, whereas conventional designs are optimized for correct operation and recovery-driven designs are optimized for a specific target error rate.…”

Section: Implications For Circuits and Architecturesmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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138

116

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Abstract-Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure yield and reliability with respect to a rigid set of datasheet specifications. This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software. This leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or modeled hardware. The envisioned underdesigned and opportunistic computing (UnO) machines face a number of challenges related to the sensing infrastructure and software interfaces that can effectively utilize the sensory data. In this paper, we outline specific sensing mechanisms that we have developed and their potential use in building UnO machines.

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Section: Implications For Circuits and Architecturesmentioning

confidence: 99%

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Gupta

Agarwal

Dolecek

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

138

116

View full text Add to dashboard Cite

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“…errors without a hardware fail-safe [31]. Our workloads do not fall into this criteria, therefore we target the more general case where hardware robustness is a must.…”

Section: B Designing For Typical-case Operationmentioning

confidence: 99%

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel R Core TM 2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

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“…Several factors such as the limited perceptual capability of humans allow imprecision in the numerical exactness of the computation in these applications. This freedom can be exploited in the implementation of the applications by achieving significant improvements in terms of performance and energy efficiency in comparison to the exact implementation [2,4,15]. Several approaches for mathematical analyses related to imperfect computation have been proposed which are heavily used in the implementation of approximate computing [2].…”

Section: Introductionmentioning

confidence: 99%

BDD minimization for approximate computing

Soeken

Grobe

Chandrasekharan

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-We present Approximate BDD Minimization (ABM) as a problem that has application in approximate computing.Given a BDD representation of a multi-output Boolean function, ABM asks whether there exists another function that has a smaller BDD representation but meets a threshold w.r.t. an error metric. We present operators to derive approximated functions and present algorithms to exactly compute the error metrics directly on the BDD representation. An experimental evaluation demonstrates the applicability of the proposed approaches.

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Stochastic computation

Cited by 122 publications

References 20 publications

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

BDD minimization for approximate computing

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