Statistical IC simulation based on independent wafer extracted process parameters and experimental designs

Davis, William F.; Ida, R.

doi:10.1109/bipol.1989.69505

Cited by 25 publications

(9 citation statements)

References 6 publications

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“…These are mapped into the SPICE BJT model parameters following the approach first presented by Davis and Ida. 7 There are three measures of device performance to fitÀ Àthat are both key for IC design and that make r sbe , ÁLe, and J bei observable: the base-emitter voltage V bes , which gives a defined collector current (this is equivalent to the collector current at a fixed base-emitter bias); the forward Early voltage V af (note that this is extracted from measurements, and is not the SPICE model parameter); and b. Table 1 shows measured manufacturing data along with summary statistics from a 10,000-sample Monte Carlo simulation using statistical models, generated from the BPV procedure, based on both linear and quadratic e(p) formulations.…”

Section: Extended Bpv Resultsmentioning

confidence: 99%

“…Appropriate mappings from independent process parameters into correlated SPICE BJT model parameters were first reported by Davis and Ida. 7 Our experience is that it is always possible to use physical analysis to determine a set of independent process parameters (p), and the mappings from these into SPICE model parameters, which control device performance.…”

Section: Compact Variability Modeling For Nanometer Cmos Technologymentioning

confidence: 99%

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Extensions to Backward Propagation of Variance for Statistical Modeling

McAndrew¹,

Stevanović

et al. 2010

IEEE Des. Test. Comput.

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STATISTICAL SIMULATION IS IMPORTANT for the design of high-yield circuits, 1 and statistical simulation requires statistical models. Such models can be generated using numerical techniques such as principal component analysis or factor analysis. 2,3 However, physical models have proven substantially more accurate and efficient than strictly numerical models for retargeting statistical models (both for mean shifts and variance shifts in a process), predicting statistical models for a process based on previous generations of that process, and capturing unexpected or anomalous behavior in statistical variations over bias or geometry. The backward propagation of variance (BPV) technique is a unified approach for physically based statistical modeling, for both global and local (mismatch) statistical variations. 4,5 In this article, we present recent extensions and enhancements to the BPV technique. We show how the assumption of a linear dependence of electrical performance on process parameters can be relaxed, and that correlations between different electrical performances can be explicitly included in the procedure. We include measures of circuit performance as modeling targets, andshow that overspecifying the electrical performances to be modeled can improve overall statistical-modeling accuracy.

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Section: Extended Bpv Resultsmentioning

confidence: 99%

Section: Compact Variability Modeling For Nanometer Cmos Technologymentioning

confidence: 99%

Extensions to Backward Propagation of Variance for Statistical Modeling

McAndrew¹,

Stevanović

et al. 2010

IEEE Des. Test. Comput.

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“…To overcome the deficiencies from the extraction of electrical parameters, a technique that describes electrical characteristics using physical or process parameters has been developed [2].…”

Section: Modeling Of Component Electrical Parameters By Independent Pmentioning

confidence: 99%

“…'wc--T-K, [ BFt = f(x,y,a,b, ..) RB = f(x,y.a,b...) I 'L',,Emit~jr.J ts n IS2 = f(x,y,a,b,...) SubstrateI BF2=f(x,y,a,b,...Method and test structure for extracting variations m lateral PNP transistor base width[2].…”

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confidence: 99%

Analog statistical simulation for bipolar integrated circuits

Rencher¹

1991

Analog Integr Circ Sig Process

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Analog circuit design automation continues to gain attention in methods to improve, automate, and reduce design cycle time. These techniques address the needs of improving design for functionality, however the importance of design for manufacturability continues to be neglected. The emphasis of design for manufacturability is shown when the quality of a part is measured. Parts designed with no consideration for process/design variations result in poor yield. To address the need in analog design for manufacturability, new techniques that involve the areas of physical process, geometric modeling of electrical parameters, and statistical simulation techniques using independent process parameters, yield and Cpk analysis are defined and implemented. Results from these techniques provide the analog designer with the ability to simulate and predict circuit quality with process and design variations. To support the defined techniques, a design tool called MSTAT (Motorola Statistical Analysis Tool) is developed. Results of these techniques accompanied with MSTAT output is presented.

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“…A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry.…”

mentioning

confidence: 99%

A method for modeling the manufacturability of IC designs

Boskin¹,

Spanos²,

Korsh³

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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A methodology for modeling the manufacturability of MOS transistors and circuits has been developed. The models are based on a small set of measurable process characterization parameters, whose variation explains the range of performance seen during production. A statistical MOSFET model, based on these measurable process parameters, was developed using global optimization and regression modeling of key fitting parameters to accurately predict transistor characteristics over a wide range of process variation. These same process parameters can be measured on the manufacturing floor, both in-line and at electrical test, and used to predict the performance of the fabricated integrated circuit before packaging and final test. The models for use in manufacturing and design are integrated, and data taken from the manufacturing line can be used to identify process shifts as well as to suggest design improvements for manufacturability enhancement. IntroductionIn today's competitive semiconductor manufacturing environment, it is important to be able to anticipate the effects of processing variation while still designing the product, and to characterize and control this variation while producing it [1,2]. In this work we present a methodology for modeling IC performance in terms of a simple set of process characterization data. First, a MOSFET model is developed, which utilizes a set of process parameters to predict transistor performance across the range of process variation seen on the fabrication line. At the design stage, the MOSFET model can be used for statistical circuit simulation in order to test the manufacturability of the design. These parameters can also be measured during production, and used to predict the performance of fabricated parts, early in the production cycle. A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry. There are several reasons for this problem which are addressed in this research.First, early work in statistical modeling relied heavily on the use of process simulation, with the accompanying prohlem of tuning the simulator to match an actual manufacturing line [6]. The method presented in this work does not rely on process simulation, but uses data collected from transistor characterization, in conjunction with straightforward device physics. Further, the use of manufacturing data ensures that the parameters are measurable using production line capable techniques, and that they explain most of the variation seen on an actual fab line.Secondly, the early statistical device models were verified by matching a...

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Statistical IC simulation based on independent wafer extracted process parameters and experimental designs

Cited by 25 publications

References 6 publications

Extensions to Backward Propagation of Variance for Statistical Modeling

Extensions to Backward Propagation of Variance for Statistical Modeling

Analog statistical simulation for bipolar integrated circuits

A method for modeling the manufacturability of IC designs

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