Statistical assessment of endurance degradation in high and low resistive states of the HfO<inf>2</inf>-based RRAM

Total Ionizing Dose Effects on TiN/Ti/HfO2/TiN Resistive Random Access Memory Studied via Electrically Detected Magnetic Resonance

“…These 200 nm by 200 nm devices are cross-point type RRAM with 5.8 nm thick HfO 2 deposited via atomic layer deposition. Additional details about the device structure has been reported elsewhere [25]. For all EDMR measurements we utilized an EDMR spectrometer with a Lakeshore magnet, Mirco-Now microwave-bridge, Stanford Preamplifier, and LabView data acquisition software.…”

A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO₂ RRAM

“…with n being the number of cycles, T RESET (T SET ) the reset (set) pulse period and T CHECK the time to verify if R is within the targeted R span. However, if the R HRS distribution changes during device operation [6], even a good initial choice of the parameters may cause the algorithm to fail. As such, this scheme is resilient to the "negative set failure" but shows no adaptability to degradation.…”

“…Moreover, we also set boundaries on V RESET to prevent over-reset and under-reset failures (V RESET,MIN =1.3V, V RESET,MAX =1.8V) [11]. The DAPV scheme allows optimizing the reset conditions according to the actual device statistical response [3][4][5], showing adaptability to R HRS distributions degradation [6].…”

“…Major concerns are cycling variability [3][4], i.e. considerable dispersion of High-Resistive (HRS) and Low-Resistive State (LRS) resistances, and resistance distributions degradation [6], i.e. changes in the stochastic response of the device over time.…”

Bipolar Resistive RAM Based on <formula formulatype="inline"> <tex Notation="TeX">${\rm HfO}_{2}$</tex> </formula>: Physics, Compact Modeling, and Variability Control

“…he research of novel non-volatile memory technologies satisfying the stringent consumer market requirements has tremendously accelerated in the last years. Among the many proposed solutions, the Resistive Random Access Memory (RRAM) technology represents an attractive option due to its potential for low-complexity, high-density, high-speed, lowcost, low-energy non-volatile operation [1][2][3][4][5][6][7][8][9], which can be exploited in both embedded and stand-alone applications. Furthermore, RRAM devices can easily be integrated in the back-end of line (BEOL) thus enabling innovative logic-inmemory approaches and easier transition toward full-3D architectures [3,9].…”