A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO&lt;sub&gt;2&lt;/sub&gt; RRAM

Puglisi, Francesco Maria; Wenger, Christian; Pavan, Paolo

doi:10.1109/led.2015.2464256

Cited by 43 publications

(28 citation statements)

References 13 publications

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“…It should be noted that a device with non-linear and/or non-symmetric resistance switching can still be used in multilevel applications if compensated for by designing a suitable pulse scheme [85,86,87], as shown in Section 3.3. With the support of the described multiscale simulations, the required pulse scheme can be co-designed with the device properties and optimized to achieve the required number of levels.…”

Section: Discussionmentioning

confidence: 99%

Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Torraca

Puglisi

Padovani³

et al. 2019

Materials

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Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many different physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diffusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material’s microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device’s performance and variability to be evaluated, the analog resistance switching to be optimized, and the device’s reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks.

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Section: Discussionmentioning

confidence: 99%

Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Torraca

Puglisi

Padovani³

et al. 2019

Materials

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“…The purpose of the BCMS is not only to obtain tight distributions of multiple conductance levels in the full switching window, but also to unify the initial state for one group of tested devices to explore the retention and endurance degradation behaviors of analog RRAM for neuromorphic computing. Some representative verification schemes were reported to control conductance windows for binary RRAM [14]- [17]. However, compared with previous these works, the BCMS has differences from three aspects: 1) Automatic bi-directional operations (both SET and RESET); 2) Tight conductance distributions of all the conductance levels in analog RRAM; 3) Multiple devices are adapted simultaneously, and only the cells which are successfully programmed in the designed conductance range are marked and will be measured in the following retention test.…”

Section: Device and Measurements Methodsmentioning

confidence: 99%

Endurance and Retention Degradation of Intermediate Levels in Filamentary Analog RRAM

Zhao

Gao

et al. 2019

IEEE J. Electron Devices Soc.

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The understanding of the retention and endurance degradation behavior of different levels of filamentary analog RRAM is critical for the development of the neuromorphic computing. This paper investigates the conductance distribution of different levels during retention and endurance tests. The low conductance states and high conductance states change from the normal distribution at the beginning to asymmetric skewed distribution with baking time increasing. But intermediate states remain the normal distribution. A model is proposed to predict the conductance evolution of different levels. It is also found that endurance lifetime depends on the ratio and position of endurance window. The longer endurance lifetime is attributed to switching in a smaller high-C window. Physical mechanism of endurance degradation is discussed.

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“…The ISPVA method mentioned in the previous section is in the category of writeverification method. Both methods also enable multi-level programming of the ReRAM cells (Lieske et al, 2018;Puglisi et al, 2015). This work models a write-verification method that is the most common practice for memory design.…”

Section: Trade-offs In Writing Parameter Selectionsmentioning

confidence: 99%

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

Hosseinzadeh

Biglari

Fey

2021

Front. Nanotechnol.

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Non-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on resistive random access memories (ReRAMs), phase-change memories, or spin-transfer torque random access memories will replace conventional memory technologies in certain areas or complement them in hybrid solutions. To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore, we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in the circuit level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely, serial read and parallel read. They are extensively studied and compared in this work, as well as the write-verification method that is often used in NVMs to reduce the device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed, which is capable of performing energy, performance, and area estimation for a given setup. In this work, three case studies were conducted, namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse width variation and their energy latency trade-off for the write-verification method in ReRAM.

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A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO<sub>2</sub> RRAM

Cited by 43 publications

References 13 publications

Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Multiscale Modeling for Application-Oriented Optimization of Resistive Random-Access Memory

Endurance and Retention Degradation of Intermediate Levels in Filamentary Analog RRAM

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

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