Statistical aspects of NBTI/PBTI and impact on SRAM yield

Asenov, A.; Brown, Andrew R.; Cheng, Binjie

doi:10.1109/date.2011.5763240

Cited by 6 publications

(3 citation statements)

References 14 publications

(22 reference statements)

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“…NBTI has proven to be a major reliability concern for deeply scaled transistors [1]- [3] which can severely affect the working of digital & analog circuits [4]. To address the Negative Bias Temperature Instability (NBTI) issue at circuit level, one standard approach is based on the modeling of the NBTI degradation measured at transistor level stressed under simple AC mode.…”

Section: Introductionmentioning

confidence: 99%

A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

Subirats¹,

Garros²,

Cluzel³

et al. 2014

2014 IEEE International Reliability Physics Symposium

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In this paper, we develop a new "recovery free" measurement technique able to apply arbitrary NBTI stress patterns of '1' & '0' on the gate of the transistor. This technique is very useful to evaluate the BTI degradation seen by the device in circuit conditions. With this method, it is shown that the NBTI shift does not depend on the bit arrangement within a sequence for bit length <1µs but only on the overall circuit activity. Such a result validates the standard approach based on regular AC stress to address NBTI concern at circuit level. Furthermore, all the revisited results obtained with our new measurement technique are successfully modeled using a dedicated numerical RC model. It gives new insights on the physical mechanisms responsible for NBTI in advanced nodes.

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Section: Introductionmentioning

confidence: 99%

A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

Subirats¹,

Garros²,

Cluzel³

et al. 2014

2014 IEEE International Reliability Physics Symposium

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“…The MOSFET transistors are deteriorated by aging mechanisms like hot-carrier injection (HCI), radiation induced damage, and bias temperature instability (BTI). With the introduction of high-k transistor gates, the nMOS transistor becomes sensitive to the PBTI (positive BTI) effect [13], [14]. Several works have studied the effects of PBTI on the reliability of the SRAM cell - [15], [16] among othersbut limited publications are available on evaluating its effect on STT-MRAMs.…”

Section: Introductionmentioning

confidence: 99%

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs

Carlo

Indaco

Prinetto

et al. 2014

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.Postprint (published version

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“…[17][18][19] Furthermore, P/NBTI-related variability is determined by discrete charge trapping of the random discrete dopants. [20][21][22][23][24][25] Studies of a model for variability is developed and used to derive cumulative distribution functions (CDFs) for device bias and geometry applications. 18,26,27) However, experimental investigations of I d-RTS and its reliability have not yet been fully clarified, although studies on device performance and the reliability of advanced HK dielectric CMOSFETs have been widely carried out.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Positive and Negative Bias Temperature Instability of High-κ Dielectric Metal Gate Metal–Oxide–Semiconductor-Field-Effect-Transistors by Random Telegraph Signal

Huang

Gong

Huang

2013

Jpn. J. Appl. Phys.

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We investigate the impact of positive and negative bias temperature instability (P/NBTI) on the current degradation by using the drain current random telegraph signal (I dRTS) in high-κ gate dielectric and metal-gate MOSFETs. The samples were stressed at typical BTI oxide electric field (∼7 MV/cm) and I dRTS amplitude (ΔI dRTS) distributions were measured before and after P/NBTI stress. It is shown that I dRTS degradation (ΔI dRTS/I dRTS) in NBTI devices exhibits a wider amplitude distribution than the PBTI one. In addition, we trace trapped charge-induced saturation current I Dsat degradation in P/NBTI stress. As a result, the statistical analysis indicates that ΔI Dsat/I Dsat of the p-MOSFET is larger than ΔI Dsat/I Dsat of the n-MOSFET. Moreover, the lifetime of the device is numerically estimated based on current degradation with or without RTS. We consequently found that P/NBTI lifetime comes worse by considering the effect of RTS.

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Statistical aspects of NBTI/PBTI and impact on SRAM yield

Cited by 6 publications

References 14 publications

A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

Reliability estimation at block-level granularity of spin-transfer-torque MRAMs

Investigation of Positive and Negative Bias Temperature Instability of High-κ Dielectric Metal Gate Metal–Oxide–Semiconductor-Field-Effect-Transistors by Random Telegraph Signal

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