Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs From MCUs

Abstract

Abstract-Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

“…Results at nominal voltage (3.3V, Round H), which were carried out in previous tests in 2013 for a sample of the same batch [15], have also been included in Table I as reference. In that occasion, SRAMs were set at a fairly large distance from the target (40 cm), to limit the neutron flux to approximately 3 × 10 4 n·cm −2 ·s −1 .…”

“…• The utilization of the proprietary unscrambling information of Cypress to accurately discern SBUs/MCUs instead of the probabilistic methodology presented in [15].…”

Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests

“…Recently, in [16] the authors needed to determine the ratio between false and actual 2-bit MCU. They identified pairs with the IND with D = 1 and proposed an expression quite similar to (6) although an erroneous additional factor of 2 was added due to not having correctly counted the number of SBU pairs. At any rate, the conclusions of this manuscript are by no means invalidated.…”

“…The second option consists in combining logical addresses in pairs (e.g., XORing [4] or subtracting [5]) to detect the resulting values that occur more often than expected and, thus, pointing out to the existence of potential MCUs. Anomalously repeated values are used to combine addresses in pairs and, this way, discover hidden related bitflips [6], [7]. The main advantage of this technique is that it is not necessary to have access to any proprietary information about the memory layout.…”

“…Finally, there also exist the so-called "statistical methods", in which anomalies in the characteristics of the pairs of hit addresses need to be discovered. Two examples [6], [7] (7), (9), and (10), respectively.…”