Inherent Uncertainty in the Determination of Multiple Event Cross Sections in Radiation Tests

Abstract

In radiation tests on SRAMs or FPGAs, two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests such as the "birthday statistics" have been proposed to estimate the accuracy of the experimental results. In this paper, simple formulae are proposed to determine the expected number of false 2-bit and 3-bit MCUs from the number of bitflips, memory size and the method used to search multiple events. These expressions are validated using Monte Carlo simulations and experimental data. Also, a technique is proposed to refine experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment.

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

“…N BF being the number of bitflips, W the data wordwidth, and L N the memory size in bits. The inner term inside the exponential function is just the expected number of false 2-bit MBUs and a similar expression can be used to determine the number of false 3-bit ones [17], [18]. The rightwards columns in Table II show the expected number of false MBUs as well as the probability of occurring at least a false MBU of any multiplicity with W = 32, L N = N ′ CF .…”

“…It is important, in any case, to determine if these events are actual or false, due to the random occurrence of bitflips in neighbor cells. In [18], it has been proposed that the average number of false 2-bit MCUs for this technique is m R · N BF · (N BF − 1) /L N , m R being the number of critical DV distances used to relate pairs of addresses. In the worst case (TM5), this number is only 0.13, much lower than the actual value for this test (105).…”

Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

“…Since there seems to be a correlation between the total number of bitflips in a round of reading and the appearance of these particular MCUs, it was suspected that some (or maybe all) of these events were a consequence of independent SBUs that coincidentally affected close SRAM bitcells and therefore, they were erroneously considered as part of the same multiple event. In previous works [23], [24], the authors studied that the probability of observing so-called "false" multiple events becomes non negligible if the number of bitflips that occurred in the same round of reading is high enough. In particular, if Manhattan distance is used as the metric to group bitflips into the same MCU, it was postulated that the expected number of false 2-bit MCUs is:…”

“…Where N BF is the number of bitflips occurred in the experiment, M D is the threshold value of the Manhattan distance used and L N is the size of the memory in bits. This equation was developed by exploiting the idea that a given SBU has a so-called "area of influence" that is defined as the number of bitcells existing around it at a Manhattan distance lower or equal to M D. In [24], it was demonstrated that it can be obtained as:…”

“…First, Section II discusses the experimental results on the 130-nm, 90-nm and 65-nm nodes obtained with protons and neutrons, as well as the comparison with the MUSCA-SEP3 predictions. Then, Section III discusses the so-called "false multiple events" (as defined by the authors in previous works [23], [24]), which constituted a disagreement observed in Section II. Section IV presents scaling trends made with MUSCA-SEP3 simulations on more miniaturized nodes (65-nm down to 14-nm) and finally, Section V presents the conclusions.…”