Static timing analysis of embedded software on advanced processor architectures

Hergenhan, André

doi:10.1145/343647.343846

Cited by 38 publications

(13 citation statements)

References 5 publications

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“…This procedure allows a time-enhanced simulation of the original functional model concerning the target platform. The execution times of the paths that were estimated with the analysis tool GROMIT [7] can be annotated in the SystemC description by wait-instructions. The mapping between CDG and source code is performed using debug information and the consideration of structural elements like branches and loops.…”

Section: Back-annotation Of Execution Timesmentioning

confidence: 99%

“…The latencies c min , c max are attributed to each edge e cdg , which represent the execution time of the longest and shortest path between the corresponding nodes in the control-flow graph. These latencies are determined by static timing analysis [7].…”

Section: Introductionmentioning

confidence: 99%

“…This problem is illustrated inFigure 7andFigure 8. For example, the communication C 2 and C 3 inFigure 7start their execution during the time intervals [L(path min (I 2 S 2 )), L(path max (I 2 S 2 ))] =[7,15] and [L(path min (I 2 S 3 )), L(path max (I 2 S 3 ))] =[12, 26]. These time intervals are depicted in…”

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confidence: 99%

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Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

Siebenborn

Viehl

Bringmann

2007

2007 Asia and South Pacific Design Automation Conference

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In this paper, we present an approach for control-flow aware communication and conflict analysis of systems of parallel communicating processes. This approach allows to determine the global timing behavior of such a system and to detect communication that might produce conflicts on shared communication resources. Furthermore, we show the incorporation of temporal environment models in order to analyze their influence on the system behavior. Based on the determined conflicts, an automated allocation and binding approach for shared resources to resolve potential access conflicts is proposed. All analysis steps can be performed starting with a TLM SystemC model of the entire system without any need for user interaction. Finally, a SystemC model of a Viterbi decoder is used as case study to demonstrate the capability of our approach. I. INTRODUCTIONThe complexity of systems is steadily increasing and already today, there are designs integrating more than one processor core with different instruction sets, various interfaces, memories and specialized hardware onto a single chip. Already today, the interconnection and communication of the components is a key issue in the design of such systems. Many embedded systems are composed of different processors and communicate via shared resources. Embedded systems interact with their environment under more or less hard timing constraints. The communication in such systems has a strong influence on the global timing behavior. Methods are needed to analyze timing properties, average throughput, as well as worst case response time (WCRT). Currently, analysis of such systems is usually performed by simulation with the issue of incomplete coverage. Formal methods are needed to identify the corner cases. This paper describes new methods for formal analysis of safety-critical embedded applications with hard time constraints executed on multiple processors. These systems are usually statically scheduled and do not allow task preemption. However, a static schedule can be included as a process by our analysis methods. Unlike other approaches that operate on task graphs, our analysis approach can be applied directly on a given SystemC model as functional representation of the entire system without any user interaction.The influence of blocking communication on the timing of the system is considered by identifying synchronizing communication and by determining the time a process is stalled at such a communication. With this knowledge,

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Section: Back-annotation Of Execution Timesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Control-Flow Aware Communication and Conflict Analysis of Parallel Processes

Siebenborn

Viehl

Bringmann

2007

2007 Asia and South Pacific Design Automation Conference

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“…This kind of representation has a more formal semantics than the original format. The runtime of blocks between the communication events can be determined by execution time analysis of an existing behavioral description [4,2] or by user annotations originating from experiences, assumptions or the specification. The combination of UML/SysML specifications with analytical results of existing IP and libraries leads to structured reuse of qualified IP in platform based design.…”

Section: Figure 1 Analysis Flowmentioning

confidence: 99%

“…The predecessor states must consider the compatibility of the relations of the edges as defined in(4).…”

mentioning

confidence: 99%

Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design

Viehl

Schonwald

Bringmann

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative performance analysis is not adequately taken into account in early design stages of the system. In this paper, we present our approach for formal and simulation based performance analysis of systems specified with UML2/SysML. The basis of our analysis approach is the detection of communication that synchronize the control flow of the corresponding instances of the system and make the relationship explicit. Using this knowledge, we are able to determine a global timing behavior and violations of this effected by preset constraints. Hence, it is also possible to detect potential conflicts on shared communication resources if a specification of the target architecture is given. With these information it is possible to evaluate system models at an early design stage.

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